# HG changeset patch # User Frits van Bommel # Date 1236729700 -3600 # Node ID 6a19c36fc4a6886bac5c99638dd7ce829f03be5c # Parent d33b0d4b816a8f67d708fb3ae4eaf2a83bcffd71# Parent b1d75bf46ffa87e9f238ec55d811ab80add0f696 Merge diff -r d33b0d4b816a -r 6a19c36fc4a6 gen/asm-x86-32.h --- a/gen/asm-x86-32.h Tue Mar 10 12:12:24 2009 +0100 +++ b/gen/asm-x86-32.h Wed Mar 11 01:01:40 2009 +0100 @@ -209,6 +209,7 @@ Op_Fis_P, Op_Fid, Op_Fid_P, + Op_FidR_P, Op_Ffd, Op_FfdR, Op_Ffd_P, @@ -449,7 +450,8 @@ /* Op_Fis_ST */ { mem, 0, 0, FPInt_Types, Clb_ST }, // " /* Op_Fis_P */ { mem, 0, 0, FPInt_Types, Clb_ST }, // push and pop, fild so also 64 bit /* Op_Fid */ { D|mem, 0, 0, FPInt_Types }, // only 16bit and 32bit, DMD defaults to 16bit - /* Op_Fid_P */ { D|mem, 0, 0, FPInt_Types, Clb_ST }, // push and pop, fild so also 64 bit + /* Op_Fid_P */ { D|mem, 0, 0, FPInt_Types, Clb_ST, Next_Form, Op_FidR_P }, // push and pop, fild so also 64 bit + /* Op_FidR_P */ { D|mem,rfp, 0, 0, FPInt_Types, Clb_ST }, // push and pop, fild so also 64 bit /* Op_Ffd */ { D|mfp, 0, 0, FP_Types, 0, Next_Form, Op_FfdR }, // only 16bit and 32bit, DMD defaults to 16bit, reg form doesn't need type /* Op_FfdR */ { D|rfp, 0, 0 }, /* Op_Ffd_P */ { D|mfp, 0, 0, FP_Types, Clb_ST, Next_Form, Op_FfdR_P }, // pop, fld so also 80 bit, " @@ -1377,7 +1379,15 @@ } if ( token->value == TOKcomma ) + { nextToken(); + } + else if ( token->value == TOKint16 || token->value == TOKint32 ) + { + //throw away the 'short' in "jle short label;". Works for 'long' also. + operands[0] = operands[1]; + return; + } else if ( token->value != TOKeof ) { ok = false; @@ -1749,13 +1759,25 @@ if ( operands[0].dataSize == Far_Ptr ) // %% type=Far_Ptr not set by Seg:Ofss OTOH, we don't support that.. insnTemplate->writebyte ( 'l' ); } - else if ( op == Op_fxch || op == Op_FfdRR_P) + else if ( op == Op_fxch || op == Op_FfdRR_P || op == Op_FidR_P ) { + if ( operands[0].cls == Opr_Mem && op == Op_FidR_P ) + { + nOperands = 1; + } // gas won't accept the two-operand form - if ( operands[1].cls == Opr_Reg && operands[1].reg == Reg_ST ) + else if ( operands[1].cls == Opr_Reg && operands[1].reg == Reg_ST ) { nOperands = 1; } + else if ( operands[1].cls == Opr_Mem && operands[1].reg == Reg_ST || operands[0].cls == Opr_Mem ) + { + nOperands = 1; + } + else if ( operands[0].cls == Opr_Reg && (operands[0].reg == Reg_ST || operands[0].reg == Reg_ST1 )) + { + //fix previous update to allow single operand form of fstp + } else { stmt->error ( "invalid operands" ); @@ -2784,6 +2806,10 @@ ident = Id::__dollar; goto do_dollar; break; + case TOKint16: + case TOKint32: + //This if for the 'short' in "jle short Label;" + return Handled; default: invalidExpression(); return Handled; diff -r d33b0d4b816a -r 6a19c36fc4a6 gen/asm-x86-64.h --- a/gen/asm-x86-64.h Tue Mar 10 12:12:24 2009 +0100 +++ b/gen/asm-x86-64.h Wed Mar 11 01:01:40 2009 +0100 @@ -17,7 +17,7 @@ Reg_EDI, Reg_EBP, Reg_ESP, - Reg_ST, + Reg_ST, Reg_ST0, Reg_ST1, Reg_ST2, Reg_ST3, Reg_ST4, Reg_ST5, Reg_ST6, Reg_ST7, Reg_MM0, Reg_MM1, Reg_MM2, Reg_MM3, Reg_MM4, Reg_MM5, Reg_MM6, Reg_MM7, Reg_XMM0, Reg_XMM1, Reg_XMM2, Reg_XMM3, Reg_XMM4, Reg_XMM5, Reg_XMM6, Reg_XMM7, @@ -45,7 +45,7 @@ Reg_TR3, Reg_TR4, Reg_TR5, Reg_TR6, Reg_TR7 } Reg; - static const int N_Regs = /*gp*/ 8 + /*fp*/ 8 + /*mmx*/ 8 + /*sse*/ 8 + + static const int N_Regs = /*gp*/ 8 + /*fp*/ 9 + /*mmx*/ 8 + /*sse*/ 8 + /*seg*/ 6 + /*16bit*/ 8 + /*8bit*/ 8 + /*sys*/ 4+6+5 + /*flags*/ + 1 + 8 /*RAX, etc*/ + 8 /*R8-15*/ @@ -78,6 +78,7 @@ { "EBP", NULL_TREE, NULL, 4, Reg_EBP }, { "ESP", NULL_TREE, NULL, 4, Reg_ESP }, { "ST", NULL_TREE, NULL, 10, Reg_ST }, + { "ST(0)", NULL_TREE, NULL, 10, Reg_ST0 }, { "ST(1)", NULL_TREE, NULL,10, Reg_ST1 }, { "ST(2)", NULL_TREE, NULL,10, Reg_ST2 }, { "ST(3)", NULL_TREE, NULL,10, Reg_ST3 }, @@ -283,6 +284,7 @@ Op_Fis_P, Op_Fid, Op_Fid_P, + Op_FidR_P, Op_Ffd, Op_FfdR, Op_Ffd_P, @@ -523,7 +525,8 @@ /* Op_Fis_ST */ { mem, 0, 0, FPInt_Types, Clb_ST }, // " /* Op_Fis_P */ { mem, 0, 0, FPInt_Types, Clb_ST }, // push and pop, fild so also 64 bit /* Op_Fid */ { D|mem, 0, 0, FPInt_Types }, // only 16bit and 32bit, DMD defaults to 16bit - /* Op_Fid_P */ { D|mem, 0, 0, FPInt_Types, Clb_ST }, // push and pop, fild so also 64 bit + /* Op_Fid_P */ { D|mem, 0, 0, FPInt_Types, Clb_ST, Next_Form, Op_FidR_P }, // push and pop, fild so also 64 bit + /* Op_FidR_P */ { D|mem,rfp,0, 0, FPInt_Types, Clb_ST }, // push and pop, fild so also 64 bit /* Op_Ffd */ { D|mfp, 0, 0, FP_Types, 0, Next_Form, Op_FfdR }, // only 16bit and 32bit, DMD defaults to 16bit, reg form doesn't need type /* Op_FfdR */ { D|rfp, 0, 0 }, /* Op_Ffd_P */ { D|mfp, 0, 0, FP_Types, Clb_ST, Next_Form, Op_FfdR_P }, // pop, fld so also 80 bit, " @@ -1546,7 +1549,7 @@ classifyOperand ( & operands[i] ); while ( 1 ) - { + { if ( nOperands == opInfo->nOperands() ) { wrong_number = false; @@ -1883,13 +1886,21 @@ if ( operands[0].dataSize == Far_Ptr ) // %% type=Far_Ptr not set by Seg:Ofss OTOH, we don't support that.. insnTemplate->writebyte ( 'l' ); } - else if ( op == Op_fxch || op == Op_FfdRR_P) + else if ( op == Op_fxch || op == Op_FfdRR_P || op == Op_FidR_P ) { - // gas won't accept the two-operand form - if ( operands[1].cls == Opr_Reg && operands[1].reg == Reg_ST ) + if ( operands[0].cls == Opr_Mem && op == Op_FidR_P ) { nOperands = 1; } + // gas won't accept the two-operand form + else if ( operands[1].cls == Opr_Reg && operands[1].reg == Reg_ST ) + { + nOperands = 1; + } + else if ( operands[0].cls == Opr_Reg && (operands[0].reg == Reg_ST1 || operands[0].reg == Reg_ST || operands[0].reg == Reg_ST0 )) + { + //fix previous update to to allow single operand form of fstp + } else { stmt->error ( "invalid operands" ); @@ -1998,6 +2009,7 @@ operand it would work... In any case, clobbering all FP prevents incorrect code generation. */ asmcode->regs[Reg_ST] = true; + asmcode->regs[Reg_ST0] = true; asmcode->regs[Reg_ST1] = true; asmcode->regs[Reg_ST2] = true; asmcode->regs[Reg_ST3] = true;