# HG changeset patch
# User thomask
# Date 1148487867 0
# Node ID 7ee2442b6bf4c77fb8e571a89cef4ae7e4996ed8
# Parent  a4b91ec616fab616eb5e0f204e5b612ed67ea769
inline ASM review

diff -r a4b91ec616fa -r 7ee2442b6bf4 run/a/asm_pshufhw_01_A.d
--- a/run/a/asm_pshufhw_01_A.d	Wed May 24 16:24:07 2006 +0000
+++ b/run/a/asm_pshufhw_01_A.d	Wed May 24 16:24:27 2006 +0000
@@ -31,7 +31,7 @@
 		if(c[0] != 4){
 			assert(0);
 		}
-		if(c[1] != 4){
+		if(c[1] != 3){
 			assert(0);
 		}
 		if(c[2] != 2){
diff -r a4b91ec616fa -r 7ee2442b6bf4 run/a/asm_pslld_01_A.d
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/run/a/asm_pslld_01_A.d	Wed May 24 16:24:27 2006 +0000
@@ -0,0 +1,53 @@
+// $HeadURL$
+// $Date$
+// $Author$
+
+module dstress.run.a.asm_pslld_01_A;
+
+version(D_InlineAsm_X86){
+	version = runTest;
+}else version(D_InlineAsm_X86_64){
+	version = runTest;
+}
+
+version(runTest){
+	import addon.cpuinfo;
+
+	int main(){
+		haveSSE2!()();
+
+		const uint[4] A = [
+			(1 << 31) | 1,
+			(1 << 31) | (1 << 7),
+			(1 << 31) | (1 << 15),
+			(1 << 31) | (1 << 23)];
+
+		const long[2] B = [0x8FFF_FFFF_FFFF_FFFF, 1];
+		uint[4] c;
+
+		asm{
+			movdqu XMM0, A;
+			movdqu XMM1, B;
+			pslld XMM0, XMM1;
+			movdqu c, XMM0;
+		}
+
+		if(c[0] != (1 << 2)){
+			assert(0);
+		}
+		if(c[1] != (1 << 8)){
+			assert(0);
+		}
+		if(c[2] != (1 << 15)){
+			assert(0);
+		}
+		if(c[3] != (1 << 24)){
+			assert(0);
+		}
+
+		return 0;
+	}
+}else{
+	pragma(msg, "DSTRESS{XFAIL}: no inline ASM support");
+	static assert(0);
+}
diff -r a4b91ec616fa -r 7ee2442b6bf4 run/a/asm_pslld_01_B.d
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/run/a/asm_pslld_01_B.d	Wed May 24 16:24:27 2006 +0000
@@ -0,0 +1,51 @@
+// $HeadURL$
+// $Date$
+// $Author$
+
+module dstress.run.a.asm_pslld_01_B;
+
+version(D_InlineAsm_X86){
+	version = runTest;
+}else version(D_InlineAsm_X86_64){
+	version = runTest;
+}
+
+version(runTest){
+	import addon.cpuinfo;
+
+	int main(){
+		haveSSE2!()();
+
+		const uint[4] A = [
+			(1 << 31) | 1,
+			(1 << 31) | (1 << 7),
+			(1 << 31) | (1 << 15),
+			(1 << 31) | (1 << 23)];
+
+		uint[4] c;
+
+		asm{
+			movdqu XMM0, A;
+			pslld XMM0, 1;
+			movdqu c, XMM0;
+		}
+
+		if(c[0] != (1 << 2)){
+			assert(0);
+		}
+		if(c[1] != (1 << 8)){
+			assert(0);
+		}
+		if(c[2] != (1 << 15)){
+			assert(0);
+		}
+		if(c[3] != (1 << 24)){
+			assert(0);
+		}
+
+		return 0;
+	}
+}else{
+	pragma(msg, "DSTRESS{XFAIL}: no inline ASM support");
+	static assert(0);
+}
diff -r a4b91ec616fa -r 7ee2442b6bf4 run/a/asm_pslldq_01_A.d
--- a/run/a/asm_pslldq_01_A.d	Wed May 24 16:24:07 2006 +0000
+++ b/run/a/asm_pslldq_01_A.d	Wed May 24 16:24:27 2006 +0000
@@ -14,22 +14,23 @@
 	import addon.cpuinfo;
 
 	int main(){
-		const ubyte[16] A = [1, 0, 2, 3, 4, 5, 6, 7, 8 ,9, 0xA, 0xB, 0xC, 0xD, 0xE, 0xF];
-		ubyte[16] b;
-		
+		haveSSE2!()();
+
+		const ulong[2] A = [(1 << 63) | 1, (1 << 63) | 3];
+		const long[2] B = [8, 1];
+		ulong[2] c;
+
 		asm{
 			movdqu XMM0, A;
-			pslldq XMM0, 1;
-			movdqu b, XMM0;
+			movdqu XMM1, B;
+			pslldq XMM0, XMM1;
+			movdqu c, XMM0;
 		}
 
-		foreach(size_t i, ubyte x; b[0 .. b.length - 1]){
-			if(x != i){
-				assert(0);
-			}
+		if(c[0] != 3){
+			assert(0);
 		}
-
-		if(b[$-1] != 0){
+		if(c[1] != 6){
 			assert(0);
 		}
 
diff -r a4b91ec616fa -r 7ee2442b6bf4 run/a/asm_psllq_01_A.d
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/run/a/asm_psllq_01_A.d	Wed May 24 16:24:27 2006 +0000
@@ -0,0 +1,42 @@
+// $HeadURL$
+// $Date$
+// $Author$
+
+module dstress.run.a.asm_psllq_01_A;
+
+version(D_InlineAsm_X86){
+	version = runTest;
+}else version(D_InlineAsm_X86_64){
+	version = runTest;
+}
+
+version(runTest){
+	import addon.cpuinfo;
+
+	int main(){
+		haveSSE2!()();
+
+		const ulong[2] A = [(1 << 63) | 3, (1 << 63) | 5];
+		const long[2] B = [8, 1];
+		ulong[2] c;
+
+		asm{
+			movdqu XMM0, A;
+			movdqu XMM1, B;
+			psllq XMM0, XMM1;
+			movdqu c, XMM0;
+		}
+
+		if(c[0] != 6){
+			assert(0);
+		}
+		if(c[1] != 10){
+			assert(0);
+		}
+
+		return 0;
+	}
+}else{
+	pragma(msg, "DSTRESS{XFAIL}: no inline ASM support");
+	static assert(0);
+}
diff -r a4b91ec616fa -r 7ee2442b6bf4 run/a/asm_psllq_01_B.d
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/run/a/asm_psllq_01_B.d	Wed May 24 16:24:27 2006 +0000
@@ -0,0 +1,40 @@
+// $HeadURL$
+// $Date$
+// $Author$
+
+module dstress.run.a.asm_psllq_01_B;
+
+version(D_InlineAsm_X86){
+	version = runTest;
+}else version(D_InlineAsm_X86_64){
+	version = runTest;
+}
+
+version(runTest){
+	import addon.cpuinfo;
+
+	int main(){
+		haveSSE2!()();
+
+		const ulong[2] A = [(1 << 63) | 3, (1 << 63) | 5];
+		ulong[2] b;
+
+		asm{
+			movdqu XMM0, A;
+			psllq XMM0, 1;
+			movdqu b, XMM0;
+		}
+
+		if(b[0] != 6){
+			assert(0);
+		}
+		if(b[1] != 10){
+			assert(0);
+		}
+
+		return 0;
+	}
+}else{
+	pragma(msg, "DSTRESS{XFAIL}: no inline ASM support");
+	static assert(0);
+}
diff -r a4b91ec616fa -r 7ee2442b6bf4 run/a/asm_psllw_01_A.d
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/run/a/asm_psllw_01_A.d	Wed May 24 16:24:27 2006 +0000
@@ -0,0 +1,60 @@
+// $HeadURL$
+// $Date$
+// $Author$
+
+module dstress.run.a.asm_psllw_01_A;
+
+version(D_InlineAsm_X86){
+	version = runTest;
+}else version(D_InlineAsm_X86_64){
+	version = runTest;
+}
+
+version(runTest){
+	import addon.cpuinfo;
+
+	int main(){
+		haveSSE2!()();
+
+		const short[8] A = [1, 4, 2, 8, 5, 3, 7, 9];
+		const long[2] B = [8, 1];
+		short[8] c;
+
+		asm{
+			movdqu XMM0, A;
+			movdqu XMM1, B;
+			psllw XMM0, XMM1;
+			movdqu c, XMM0;
+		}
+
+		if(c[0] != 2){
+			assert(0);
+		}
+		if(c[1] != 8){
+			assert(0);
+		}
+		if(c[2] != 4){
+			assert(0);
+		}
+		if(c[3] != 16){
+			assert(0);
+		}
+		if(c[4] != 10){
+			assert(0);
+		}
+		if(c[5] != 6){
+			assert(0);
+		}
+		if(c[6] != 14){
+			assert(0);
+		}
+		if(c[7] != 18){
+			assert(0);
+		}
+
+		return 0;
+	}
+}else{
+	pragma(msg, "DSTRESS{XFAIL}: no inline ASM support");
+	static assert(0);
+}
diff -r a4b91ec616fa -r 7ee2442b6bf4 run/a/asm_psllw_01_B.d
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/run/a/asm_psllw_01_B.d	Wed May 24 16:24:27 2006 +0000
@@ -0,0 +1,58 @@
+// $HeadURL$
+// $Date$
+// $Author$
+
+module dstress.run.a.asm_psllw_01_B;
+
+version(D_InlineAsm_X86){
+	version = runTest;
+}else version(D_InlineAsm_X86_64){
+	version = runTest;
+}
+
+version(runTest){
+	import addon.cpuinfo;
+
+	int main(){
+		haveSSE2!()();
+
+		const short[8] A = [1, 4, 2, 8, 5, 3, 7, 9];
+		short[8] b;
+
+		asm{
+			movdqu XMM0, A;
+			psllw XMM0, 1;
+			movdqu b, XMM0;
+		}
+
+		if(b[0] != 2){
+			assert(0);
+		}
+		if(b[1] != 8){
+			assert(0);
+		}
+		if(b[2] != 4){
+			assert(0);
+		}
+		if(b[3] != 16){
+			assert(0);
+		}
+		if(b[4] != 10){
+			assert(0);
+		}
+		if(b[5] != 6){
+			assert(0);
+		}
+		if(b[6] != 14){
+			assert(0);
+		}
+		if(b[7] != 18){
+			assert(0);
+		}
+
+		return 0;
+	}
+}else{
+	pragma(msg, "DSTRESS{XFAIL}: no inline ASM support");
+	static assert(0);
+}
diff -r a4b91ec616fa -r 7ee2442b6bf4 run/a/asm_psrad_01_A.d
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/run/a/asm_psrad_01_A.d	Wed May 24 16:24:27 2006 +0000
@@ -0,0 +1,53 @@
+// $HeadURL$
+// $Date$
+// $Author$
+
+module dstress.run.a.asm_psrad_01_A;
+
+version(D_InlineAsm_X86){
+	version = runTest;
+}else version(D_InlineAsm_X86_64){
+	version = runTest;
+}
+
+version(runTest){
+	import addon.cpuinfo;
+
+	int main(){
+		haveSSE2!()();
+
+		const uint[4] A = [
+			(1 << 31) | 1,
+			(1 << 31) | (1 << 8),
+			(1 << 31) | (1 << 16),
+			(1 << 31) | (1 << 23)];
+
+		const long[2] B = [0x8FFF_FFFF_FFFF_FFFF, 1];
+		uint[4] c;
+
+		asm{
+			movdqu XMM0, A;
+			movdqu XMM1, B;
+			psrad XMM0, XMM1;
+			movdqu c, XMM0;
+		}
+
+		if(c[0] != (3 << 30)){
+			assert(0);
+		}
+		if(c[1] != ((3 << 30) | (1 << 7))){
+			assert(0);
+		}
+		if(c[2] != ((3 << 30) | (1 << 15))){
+			assert(0);
+		}
+		if(c[3] != ((3 << 30) | (1 << 22))){
+			assert(0);
+		}
+
+		return 0;
+	}
+}else{
+	pragma(msg, "DSTRESS{XFAIL}: no inline ASM support");
+	static assert(0);
+}
diff -r a4b91ec616fa -r 7ee2442b6bf4 run/a/asm_psrad_01_B.d
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/run/a/asm_psrad_01_B.d	Wed May 24 16:24:27 2006 +0000
@@ -0,0 +1,51 @@
+// $HeadURL$
+// $Date$
+// $Author$
+
+module dstress.run.a.asm_psrad_01_B;
+
+version(D_InlineAsm_X86){
+	version = runTest;
+}else version(D_InlineAsm_X86_64){
+	version = runTest;
+}
+
+version(runTest){
+	import addon.cpuinfo;
+
+	int main(){
+		haveSSE2!()();
+
+		const uint[4] A = [
+			(1 << 31) | 1,
+			(1 << 31) | (1 << 8),
+			(1 << 31) | (1 << 16),
+			(1 << 31) | (1 << 23)];
+
+		uint[4] c;
+
+		asm{
+			movdqu XMM0, A;
+			psrad XMM0, 1;
+			movdqu c, XMM0;
+		}
+
+		if(c[0] != (1 << 30)){
+			assert(0);
+		}
+		if(c[1] != ((1 << 30) | (1 << 7))){
+			assert(0);
+		}
+		if(c[2] != ((1 << 30) | (1 << 15))){
+			assert(0);
+		}
+		if(c[3] != ((1 << 30) | (1 << 22))){
+			assert(0);
+		}
+
+		return 0;
+	}
+}else{
+	pragma(msg, "DSTRESS{XFAIL}: no inline ASM support");
+	static assert(0);
+}
diff -r a4b91ec616fa -r 7ee2442b6bf4 run/a/asm_psraw_01_A.d
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/run/a/asm_psraw_01_A.d	Wed May 24 16:24:27 2006 +0000
@@ -0,0 +1,60 @@
+// $HeadURL$
+// $Date$
+// $Author$
+
+module dstress.run.a.asm_psraw_01_A;
+
+version(D_InlineAsm_X86){
+	version = runTest;
+}else version(D_InlineAsm_X86_64){
+	version = runTest;
+}
+
+version(runTest){
+	import addon.cpuinfo;
+
+	int main(){
+		haveSSE2!()();
+
+		const short[8] A = [1, -4, 2, 8, 5, 3, 7, 9];
+		const long[2] B = [8, 1];
+		short[8] c;
+
+		asm{
+			movdqu XMM0, A;
+			movdqu XMM1, B;
+			psraw XMM0, XMM1;
+			movdqu c, XMM0;
+		}
+
+		if(c[0] != 0){
+			assert(0);
+		}
+		if(c[1] != -2){
+			assert(0);
+		}
+		if(c[2] != 1){
+			assert(0);
+		}
+		if(c[3] != 4){
+			assert(0);
+		}
+		if(c[4] != 2){
+			assert(0);
+		}
+		if(c[5] != 1){
+			assert(0);
+		}
+		if(c[6] != 3){
+			assert(0);
+		}
+		if(c[7] != 4){
+			assert(0);
+		}
+
+		return 0;
+	}
+}else{
+	pragma(msg, "DSTRESS{XFAIL}: no inline ASM support");
+	static assert(0);
+}
diff -r a4b91ec616fa -r 7ee2442b6bf4 run/a/asm_psraw_01_B.d
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/run/a/asm_psraw_01_B.d	Wed May 24 16:24:27 2006 +0000
@@ -0,0 +1,58 @@
+// $HeadURL$
+// $Date$
+// $Author$
+
+module dstress.run.a.asm_psraw_01_B;
+
+version(D_InlineAsm_X86){
+	version = runTest;
+}else version(D_InlineAsm_X86_64){
+	version = runTest;
+}
+
+version(runTest){
+	import addon.cpuinfo;
+
+	int main(){
+		haveSSE2!()();
+
+		const short[8] A = [1, -4, 2, 8, 5, 3, 7, 9];
+		short[8] c;
+
+		asm{
+			movdqu XMM0, A;
+			psraw XMM0, 1;
+			movdqu c, XMM0;
+		}
+
+		if(c[0] != 0){
+			assert(0);
+		}
+		if(c[1] != -2){
+			assert(0);
+		}
+		if(c[2] != 1){
+			assert(0);
+		}
+		if(c[3] != 4){
+			assert(0);
+		}
+		if(c[4] != 2){
+			assert(0);
+		}
+		if(c[5] != 1){
+			assert(0);
+		}
+		if(c[6] != 3){
+			assert(0);
+		}
+		if(c[7] != 4){
+			assert(0);
+		}
+
+		return 0;
+	}
+}else{
+	pragma(msg, "DSTRESS{XFAIL}: no inline ASM support");
+	static assert(0);
+}
diff -r a4b91ec616fa -r 7ee2442b6bf4 run/a/asm_psrld_01_A.d
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/run/a/asm_psrld_01_A.d	Wed May 24 16:24:27 2006 +0000
@@ -0,0 +1,53 @@
+// $HeadURL$
+// $Date$
+// $Author$
+
+module dstress.run.a.asm_psrld_01_A;
+
+version(D_InlineAsm_X86){
+	version = runTest;
+}else version(D_InlineAsm_X86_64){
+	version = runTest;
+}
+
+version(runTest){
+	import addon.cpuinfo;
+
+	int main(){
+		haveSSE2!()();
+
+		const uint[4] A = [
+			(1 << 31) | 1,
+			(1 << 31) | (1 << 8),
+			(1 << 31) | (1 << 16),
+			(1 << 31) | (1 << 23)];
+
+		const long[2] B = [0x8FFF_FFFF_FFFF_FFFF, 1];
+		uint[4] c;
+
+		asm{
+			movdqu XMM0, A;
+			movdqu XMM1, B;
+			psrld XMM0, XMM1;
+			movdqu c, XMM0;
+		}
+
+		if(c[0] != (1 << 30)){
+			assert(0);
+		}
+		if(c[1] != ((1 << 30) | (1 << 7))){
+			assert(0);
+		}
+		if(c[2] != ((1 << 30) | (1 << 15))){
+			assert(0);
+		}
+		if(c[3] != ((1 << 30) | (1 << 22))){
+			assert(0);
+		}
+
+		return 0;
+	}
+}else{
+	pragma(msg, "DSTRESS{XFAIL}: no inline ASM support");
+	static assert(0);
+}
diff -r a4b91ec616fa -r 7ee2442b6bf4 run/a/asm_psrld_01_B.d
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/run/a/asm_psrld_01_B.d	Wed May 24 16:24:27 2006 +0000
@@ -0,0 +1,52 @@
+// $HeadURL$
+// $Date$
+// $Author$
+
+module dstress.run.a.asm_psrld_01_B;
+
+version(D_InlineAsm_X86){
+	version = runTest;
+}else version(D_InlineAsm_X86_64){
+	version = runTest;
+}
+
+version(runTest){
+	import addon.cpuinfo;
+
+	int main(){
+		haveSSE2!()();
+
+		const uint[4] A = [
+			(1 << 31) | 1,
+			(1 << 31) | (1 << 8),
+			(1 << 31) | (1 << 16),
+			(1 << 31) | (1 << 23)];
+
+		const long[2] B = [0x8FFF_FFFF_FFFF_FFFF, 1];
+		uint[4] c;
+
+		asm{
+			movdqu XMM0, A;
+			psrld XMM0, 1;
+			movdqu c, XMM0;
+		}
+
+		if(c[0] != (1 << 30)){
+			assert(0);
+		}
+		if(c[1] != ((1 << 30) | (1 << 7))){
+			assert(0);
+		}
+		if(c[2] != ((1 << 30) | (1 << 15))){
+			assert(0);
+		}
+		if(c[3] != ((1 << 30) | (1 << 22))){
+			assert(0);
+		}
+
+		return 0;
+	}
+}else{
+	pragma(msg, "DSTRESS{XFAIL}: no inline ASM support");
+	static assert(0);
+}
diff -r a4b91ec616fa -r 7ee2442b6bf4 run/a/asm_psrldq_01_A.d
--- a/run/a/asm_psrldq_01_A.d	Wed May 24 16:24:07 2006 +0000
+++ b/run/a/asm_psrldq_01_A.d	Wed May 24 16:24:27 2006 +0000
@@ -4,30 +4,39 @@
 
 module dstress.run.a.asm_psrldq_01_A;
 
-int main(){
-	version(D_InlineAsm_X86){
-		const ubyte[16] a = [0, 1, 2, 3, 4, 5, 6, 7, 8 ,9, 0xA, 0xB, 0xC, 0xD, 0xE, 0xF];
-		ubyte[16] b;
-		
+version(D_InlineAsm_X86){
+	version = runTest;
+}else version(D_InlineAsm_X86_64){
+	version = runTest;
+}
+
+version(runTest){
+	import addon.cpuinfo;
+
+	int main(){
+		haveSSE2!()();
+
+		const ulong[2] A = [(1 << 63) | 1, (1 << 63) | 3];
+		const long[2] B = [8, 1];
+		ulong[2] c;
+
 		asm{
-			movdqu XMM0, a;
-			psrldq XMM0, 2;
-			movdqu b, XMM0;
+			movdqu XMM0, A;
+			movdqu XMM1, B;
+			psrldq XMM0, XMM1;
+			movdqu c, XMM0;
 		}
 
-		for(size_t i = 2; i < c.length; i++){
-			if(b[i] != i-2){
-				assert(0);
-			}
+		if(c[0] != (1 << 62)){
+			assert(0);
+		}
+		if(c[1] != (3 << 62) | 1){
+			assert(0);
 		}
 
-		if(b[0] || b[1]){
-			assert(0);
-		}
-		
 		return 0;
-	}else{
-		pragma(msg, "no Inline asm support");
-		static assert(0);
 	}
+}else{
+	pragma(msg, "DSTRESS{XFAIL}: no inline ASM support");
+	static assert(0);
 }
diff -r a4b91ec616fa -r 7ee2442b6bf4 run/a/asm_psrlq_01_A.d
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/run/a/asm_psrlq_01_A.d	Wed May 24 16:24:27 2006 +0000
@@ -0,0 +1,42 @@
+// $HeadURL$
+// $Date$
+// $Author$
+
+module dstress.run.a.asm_psrlq_01_A;
+
+version(D_InlineAsm_X86){
+	version = runTest;
+}else version(D_InlineAsm_X86_64){
+	version = runTest;
+}
+
+version(runTest){
+	import addon.cpuinfo;
+
+	int main(){
+		haveSSE2!()();
+
+		const ulong[2] A = [(1 << 63) | 3, (1 << 63) | 5];
+		const long[2] B = [8, 1];
+		ulong[2] c;
+
+		asm{
+			movdqu XMM0, A;
+			movdqu XMM1, B;
+			psrlq XMM0, XMM1;
+			movdqu c, XMM0;
+		}
+
+		if(c[0] != ((1 << 62) | 1)){
+			assert(0);
+		}
+		if(c[1] != ((1 << 62) | 2)){
+			assert(0);
+		}
+
+		return 0;
+	}
+}else{
+	pragma(msg, "DSTRESS{XFAIL}: no inline ASM support");
+	static assert(0);
+}
diff -r a4b91ec616fa -r 7ee2442b6bf4 run/a/asm_psrlw_01_A.d
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/run/a/asm_psrlw_01_A.d	Wed May 24 16:24:27 2006 +0000
@@ -0,0 +1,60 @@
+// $HeadURL$
+// $Date$
+// $Author$
+
+module dstress.run.a.asm_psrlw_01_A;
+
+version(D_InlineAsm_X86){
+	version = runTest;
+}else version(D_InlineAsm_X86_64){
+	version = runTest;
+}
+
+version(runTest){
+	import addon.cpuinfo;
+
+	int main(){
+		haveSSE2!()();
+
+		const short[8] A = [1, -4, 2, 8, 5, 3, 7, 9];
+		const long[2] B = [8, 1];
+		ushort[8] c;
+
+		asm{
+			movdqu XMM0, A;
+			movdqu XMM1, B;
+			psrlw XMM0, XMM1;
+			movdqu c, XMM0;
+		}
+
+		if(c[0] != 0){
+			assert(0);
+		}
+		if(c[1] != 0x7FFE){
+			assert(0);
+		}
+		if(c[2] != 1){
+			assert(0);
+		}
+		if(c[3] != 4){
+			assert(0);
+		}
+		if(c[4] != 2){
+			assert(0);
+		}
+		if(c[5] != 1){
+			assert(0);
+		}
+		if(c[6] != 3){
+			assert(0);
+		}
+		if(c[7] != 4){
+			assert(0);
+		}
+
+		return 0;
+	}
+}else{
+	pragma(msg, "DSTRESS{XFAIL}: no inline ASM support");
+	static assert(0);
+}
diff -r a4b91ec616fa -r 7ee2442b6bf4 run/a/asm_psrlw_01_B.d
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/run/a/asm_psrlw_01_B.d	Wed May 24 16:24:27 2006 +0000
@@ -0,0 +1,59 @@
+// $HeadURL$
+// $Date$
+// $Author$
+
+module dstress.run.a.asm_psrlw_01_B;
+
+version(D_InlineAsm_X86){
+	version = runTest;
+}else version(D_InlineAsm_X86_64){
+	version = runTest;
+}
+
+version(runTest){
+	import addon.cpuinfo;
+
+	int main(){
+		haveSSE2!()();
+
+		const short[8] A = [1, -4, 2, 8, 5, 3, 7, 9];
+		const long[2] B = [8, 1];
+		ushort[8] c;
+
+		asm{
+			movdqu XMM0, A;
+			psrlw XMM0, 1;
+			movdqu c, XMM0;
+		}
+
+		if(c[0] != 0){
+			assert(0);
+		}
+		if(c[1] != 0x7FFE){
+			assert(0);
+		}
+		if(c[2] != 1){
+			assert(0);
+		}
+		if(c[3] != 4){
+			assert(0);
+		}
+		if(c[4] != 2){
+			assert(0);
+		}
+		if(c[5] != 1){
+			assert(0);
+		}
+		if(c[6] != 3){
+			assert(0);
+		}
+		if(c[7] != 4){
+			assert(0);
+		}
+
+		return 0;
+	}
+}else{
+	pragma(msg, "DSTRESS{XFAIL}: no inline ASM support");
+	static assert(0);
+}
diff -r a4b91ec616fa -r 7ee2442b6bf4 run/a/asm_psubb_01_A.d
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/run/a/asm_psubb_01_A.d	Wed May 24 16:24:27 2006 +0000
@@ -0,0 +1,44 @@
+// $HeadURL$
+// $Date$
+// $Author$
+
+module dstress.run.a.asm_psubb_01_A;
+
+version(D_InlineAsm_X86){
+	version = runTest;
+}else version(D_InlineAsm_X86_64){
+	version = runTest;
+}
+
+version(runTest){
+	import addon.cpuinfo;
+
+	int main(){
+		haveSSE2!()();
+
+		const byte[16] A = [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, byte.min];
+		const byte[16] B = [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, byte.max];
+
+		byte[16] c;
+
+		asm{
+			movdqu XMM0, A;
+			movdqu XMM1, B;
+			psubb XMM0, XMM1;
+			movdqu c, XMM0;
+		}
+
+		foreach(byte x; c[0 .. c.length -1]){
+			if(x != 1){
+				assert(0);
+			}
+		}
+
+		if(c[c.length - 1] != 2){
+			assert(0);
+		}
+	}
+}else{
+	pragma(msg, "DSTRESS{XFAIL}: no inline ASM support");
+	static assert(0);
+}
diff -r a4b91ec616fa -r 7ee2442b6bf4 run/a/asm_psubd_01_A.d
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/run/a/asm_psubd_01_A.d	Wed May 24 16:24:27 2006 +0000
@@ -0,0 +1,44 @@
+// $HeadURL$
+// $Date$
+// $Author$
+
+module dstress.run.a.asm_psubd_01_A;
+
+version(D_InlineAsm_X86){
+	version = runTest;
+}else version(D_InlineAsm_X86_64){
+	version = runTest;
+}
+
+version(runTest){
+	import addon.cpuinfo;
+
+	int main(){
+		haveSSE2!()();
+
+		const int[4] A = [1, 2, 3, int.min];
+		const int[4] B = [0, 1, 2, int.max];
+
+		int[4] c;
+
+		asm{
+			movdqu XMM0, A;
+			movdqu XMM1, B;
+			psubd XMM0, XMM1;
+			movdqu c, XMM0;
+		}
+
+		foreach(int x; c[0 .. c.length -1]){
+			if(x != 1){
+				assert(0);
+			}
+		}
+
+		if(c[c.length - 1] != 2){
+			assert(0);
+		}
+	}
+}else{
+	pragma(msg, "DSTRESS{XFAIL}: no inline ASM support");
+	static assert(0);
+}
diff -r a4b91ec616fa -r 7ee2442b6bf4 run/a/asm_psubq_01_A.d
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/run/a/asm_psubq_01_A.d	Wed May 24 16:24:27 2006 +0000
@@ -0,0 +1,41 @@
+// $HeadURL$
+// $Date$
+// $Author$
+
+module dstress.run.a.asm_psubq_01_A;
+
+version(D_InlineAsm_X86){
+	version = runTest;
+}else version(D_InlineAsm_X86_64){
+	version = runTest;
+}
+
+version(runTest){
+	import addon.cpuinfo;
+
+	int main(){
+		haveSSE2!()();
+
+		const long[2] A = [1, long.min];
+		const long[2] B = [0, long.max];
+
+		long[2] c;
+
+		asm{
+			movdqu XMM0, A;
+			movdqu XMM1, B;
+			psubq XMM0, XMM1;
+			movdqu c, XMM0;
+		}
+
+		if(c[0] != 1){
+			assert(0);
+		}
+		if(c[1] != 2){
+			assert(0);
+		}
+	}
+}else{
+	pragma(msg, "DSTRESS{XFAIL}: no inline ASM support");
+	static assert(0);
+}
diff -r a4b91ec616fa -r 7ee2442b6bf4 run/a/asm_psubsb_01_A.d
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/run/a/asm_psubsb_01_A.d	Wed May 24 16:24:27 2006 +0000
@@ -0,0 +1,44 @@
+// $HeadURL$
+// $Date$
+// $Author$
+
+module dstress.run.a.asm_psubsb_01_A;
+
+version(D_InlineAsm_X86){
+	version = runTest;
+}else version(D_InlineAsm_X86_64){
+	version = runTest;
+}
+
+version(runTest){
+	import addon.cpuinfo;
+
+	int main(){
+		haveSSE2!()();
+
+		const byte[16] A = [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, byte.min];
+		const byte[16] B = [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, byte.max];
+
+		byte[16] c;
+
+		asm{
+			movdqu XMM0, A;
+			movdqu XMM1, B;
+			psubsb XMM0, XMM1;
+			movdqu c, XMM0;
+		}
+
+		foreach(byte x; c[0 .. c.length -1]){
+			if(x != 1){
+				assert(0);
+			}
+		}
+
+		if(c[c.length - 1] != byte.min){
+			assert(0);
+		}
+	}
+}else{
+	pragma(msg, "DSTRESS{XFAIL}: no inline ASM support");
+	static assert(0);
+}
diff -r a4b91ec616fa -r 7ee2442b6bf4 run/a/asm_psubsw_01_A.d
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/run/a/asm_psubsw_01_A.d	Wed May 24 16:24:27 2006 +0000
@@ -0,0 +1,44 @@
+// $HeadURL$
+// $Date$
+// $Author$
+
+module dstress.run.a.asm_psubsw_01_A;
+
+version(D_InlineAsm_X86){
+	version = runTest;
+}else version(D_InlineAsm_X86_64){
+	version = runTest;
+}
+
+version(runTest){
+	import addon.cpuinfo;
+
+	int main(){
+		haveSSE2!()();
+
+		const short[8] A = [1, 2, 3, 4, 5, 6, 7, short.min];
+		const short[8] B = [0, 1, 2, 3, 4, 5, 6, short.max];
+
+		short[8] c;
+
+		asm{
+			movdqu XMM0, A;
+			movdqu XMM1, B;
+			psubsw XMM0, XMM1;
+			movdqu c, XMM0;
+		}
+
+		foreach(short x; c[0 .. c.length -1]){
+			if(x != 1){
+				assert(0);
+			}
+		}
+
+		if(c[c.length - 1] != short.min){
+			assert(0);
+		}
+	}
+}else{
+	pragma(msg, "DSTRESS{XFAIL}: no inline ASM support");
+	static assert(0);
+}
diff -r a4b91ec616fa -r 7ee2442b6bf4 run/a/asm_psubusb_01_A.d
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/run/a/asm_psubusb_01_A.d	Wed May 24 16:24:27 2006 +0000
@@ -0,0 +1,44 @@
+// $HeadURL$
+// $Date$
+// $Author$
+
+module dstress.run.a.asm_psubusb_01_A;
+
+version(D_InlineAsm_X86){
+	version = runTest;
+}else version(D_InlineAsm_X86_64){
+	version = runTest;
+}
+
+version(runTest){
+	import addon.cpuinfo;
+
+	int main(){
+		haveSSE2!()();
+
+		const ubyte[16] A = [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16];
+		const ubyte[16] B = [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 19];
+
+		ubyte[16] c;
+
+		asm{
+			movdqu XMM0, A;
+			movdqu XMM1, B;
+			psubusb XMM0, XMM1;
+			movdqu c, XMM0;
+		}
+
+		foreach(byte x; c[0 .. c.length -1]){
+			if(x != 1){
+				assert(0);
+			}
+		}
+
+		if(c[c.length - 1] != 0){
+			assert(0);
+		}
+	}
+}else{
+	pragma(msg, "DSTRESS{XFAIL}: no inline ASM support");
+	static assert(0);
+}
diff -r a4b91ec616fa -r 7ee2442b6bf4 run/a/asm_psubusw_01_A.d
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/run/a/asm_psubusw_01_A.d	Wed May 24 16:24:27 2006 +0000
@@ -0,0 +1,44 @@
+// $HeadURL$
+// $Date$
+// $Author$
+
+module dstress.run.a.asm_psubusw_01_A;
+
+version(D_InlineAsm_X86){
+	version = runTest;
+}else version(D_InlineAsm_X86_64){
+	version = runTest;
+}
+
+version(runTest){
+	import addon.cpuinfo;
+
+	int main(){
+		haveSSE2!()();
+
+		const ushort[8] A = [1, 2, 3, 4, 5, 6, 7, 16];
+		const ushort[8] B = [0, 1, 2, 3, 4, 5, 6, 19];
+
+		ushort[8] c;
+
+		asm{
+			movdqu XMM0, A;
+			movdqu XMM1, B;
+			psubusw XMM0, XMM1;
+			movdqu c, XMM0;
+		}
+
+		foreach(short x; c[0 .. c.length -1]){
+			if(x != 1){
+				assert(0);
+			}
+		}
+
+		if(c[c.length - 1] != 0){
+			assert(0);
+		}
+	}
+}else{
+	pragma(msg, "DSTRESS{XFAIL}: no inline ASM support");
+	static assert(0);
+}
diff -r a4b91ec616fa -r 7ee2442b6bf4 run/a/asm_psubw_01_A.d
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/run/a/asm_psubw_01_A.d	Wed May 24 16:24:27 2006 +0000
@@ -0,0 +1,44 @@
+// $HeadURL$
+// $Date$
+// $Author$
+
+module dstress.run.a.asm_psubw_01_A;
+
+version(D_InlineAsm_X86){
+	version = runTest;
+}else version(D_InlineAsm_X86_64){
+	version = runTest;
+}
+
+version(runTest){
+	import addon.cpuinfo;
+
+	int main(){
+		haveSSE2!()();
+
+		const short[8] A = [1, 2, 3, 4, 5, 6, 7, short.min];
+		const short[8] B = [0, 1, 2, 3, 4, 5, 6, short.max];
+
+		short[8] c;
+
+		asm{
+			movdqu XMM0, A;
+			movdqu XMM1, B;
+			psubw XMM0, XMM1;
+			movdqu c, XMM0;
+		}
+
+		foreach(short x; c[0 .. c.length -1]){
+			if(x != 1){
+				assert(0);
+			}
+		}
+
+		if(c[c.length - 1] != 2){
+			assert(0);
+		}
+	}
+}else{
+	pragma(msg, "DSTRESS{XFAIL}: no inline ASM support");
+	static assert(0);
+}
diff -r a4b91ec616fa -r 7ee2442b6bf4 run/a/asm_punpckhbw_01_A.d
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/run/a/asm_punpckhbw_01_A.d	Wed May 24 16:24:27 2006 +0000
@@ -0,0 +1,86 @@
+// $HeadURL$
+// $Date$
+// $Author$
+
+module dstress.run.a.asm_punpckhbw_01_A;
+
+version(D_InlineAsm_X86){
+	version = runTest;
+}else version(D_InlineAsm_X86_64){
+	version = runTest;
+}
+
+version(runTest){
+	import addon.cpuinfo;
+
+	int main(){
+		haveSSE2!()();
+
+		const byte[16] A = [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15];
+		const byte[16] B = [0, -1, -2, -3, -4, -5, -6, -7, -8, -9, -10, -11, -12, -13, -14, -15];
+
+		byte[16] c;
+
+		asm{
+			movdqu XMM0, A;
+			movdqu XMM1, B;
+			punpckhbw XMM0, XMM1;
+			movdqu c, XMM0;
+		}
+
+		if(c[0] != 0){
+			assert(0);
+		}
+		if(c[1] != 0){
+			assert(0);
+		}
+		if(c[2] != -1){
+			assert(0);
+		}
+		if(c[3] != 1){
+			assert(0);
+		}
+		if(c[4] != -2){
+			assert(0);
+		}
+		if(c[5] != 2){
+			assert(0);
+		}
+		if(c[6] != -3){
+			assert(0);
+		}
+		if(c[7] != 3){
+			assert(0);
+		}
+		if(c[8] != -4){
+			assert(0);
+		}
+		if(c[9] != 4){
+			assert(0);
+		}
+		if(c[10] != -5){
+			assert(0);
+		}
+		if(c[11] != 5){
+			assert(0);
+		}
+		if(c[12] != -6){
+			assert(0);
+		}
+		if(c[13] != 6){
+			assert(0);
+		}
+		if(c[14] != 7){
+			assert(0);
+		}
+		if(c[15] != -7){
+			assert(0);
+		}
+
+		return 0;
+	}
+}else{
+	pragma(msg, "DSTRESS{XFAIL}: no inline ASM support");
+	static assert(0);
+}
+
diff -r a4b91ec616fa -r 7ee2442b6bf4 run/a/asm_punpckhdq_01_A.d
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/run/a/asm_punpckhdq_01_A.d	Wed May 24 16:24:27 2006 +0000
@@ -0,0 +1,50 @@
+// $HeadURL$
+// $Date$
+// $Author$
+
+module dstress.run.a.asm_punpckhdq_01_A;
+
+version(D_InlineAsm_X86){
+	version = runTest;
+}else version(D_InlineAsm_X86_64){
+	version = runTest;
+}
+
+version(runTest){
+	import addon.cpuinfo;
+
+	int main(){
+		haveSSE2!()();
+
+		const int[4] A = [0, 1, 2, 3];
+		const int[4] B = [0, -1, -2, -3];
+
+		int[4] c;
+
+		asm{
+			movdqu XMM0, A;
+			movdqu XMM1, B;
+			punpckhdq XMM0, XMM1;
+			movdqu c, XMM0;
+		}
+
+		if(c[0] != 0){
+			assert(0);
+		}
+		if(c[1] != 0){
+			assert(0);
+		}
+		if(c[2] != -1){
+			assert(0);
+		}
+		if(c[3] != 1){
+			assert(0);
+		}
+
+		return 0;
+	}
+}else{
+	pragma(msg, "DSTRESS{XFAIL}: no inline ASM support");
+	static assert(0);
+}
+
diff -r a4b91ec616fa -r 7ee2442b6bf4 run/a/asm_punpckhqdq_01_A.d
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/run/a/asm_punpckhqdq_01_A.d	Wed May 24 16:24:27 2006 +0000
@@ -0,0 +1,44 @@
+// $HeadURL$
+// $Date$
+// $Author$
+
+module dstress.run.a.asm_punpckhqdq_01_A;
+
+version(D_InlineAsm_X86){
+	version = runTest;
+}else version(D_InlineAsm_X86_64){
+	version = runTest;
+}
+
+version(runTest){
+	import addon.cpuinfo;
+
+	int main(){
+		haveSSE2!()();
+
+		const long[2] A = [1, 2];
+		const long[2] B = [-1, -2];
+
+		long[2] c;
+
+		asm{
+			movdqu XMM0, A;
+			movdqu XMM1, B;
+			punpckhqdq XMM0, XMM1;
+			movdqu c, XMM0;
+		}
+
+		if(c[0] != -1){
+			assert(0);
+		}
+		if(c[1] != 1){
+			assert(0);
+		}
+
+		return 0;
+	}
+}else{
+	pragma(msg, "DSTRESS{XFAIL}: no inline ASM support");
+	static assert(0);
+}
+
diff -r a4b91ec616fa -r 7ee2442b6bf4 run/a/asm_punpckhwd_01_A.d
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/run/a/asm_punpckhwd_01_A.d	Wed May 24 16:24:27 2006 +0000
@@ -0,0 +1,62 @@
+// $HeadURL$
+// $Date$
+// $Author$
+
+module dstress.run.a.asm_punpckhwd_01_A;
+
+version(D_InlineAsm_X86){
+	version = runTest;
+}else version(D_InlineAsm_X86_64){
+	version = runTest;
+}
+
+version(runTest){
+	import addon.cpuinfo;
+
+	int main(){
+		haveSSE2!()();
+
+		const short[8] A = [0, 1, 2, 3, 4, 5, 6, 7];
+		const short[8] B = [0, -1, -2, -3, -4, -5, -6, -7];
+
+		short[8] c;
+
+		asm{
+			movdqu XMM0, A;
+			movdqu XMM1, B;
+			punpckhwd XMM0, XMM1;
+			movdqu c, XMM0;
+		}
+
+		if(c[0] != 0){
+			assert(0);
+		}
+		if(c[1] != 0){
+			assert(0);
+		}
+		if(c[2] != -1){
+			assert(0);
+		}
+		if(c[3] != 1){
+			assert(0);
+		}
+		if(c[4] != -2){
+			assert(0);
+		}
+		if(c[5] != 2){
+			assert(0);
+		}
+		if(c[6] != -3){
+			assert(0);
+		}
+		if(c[7] != 3){
+			assert(0);
+		}
+
+		return 0;
+	}
+}else{
+	pragma(msg, "DSTRESS{XFAIL}: no inline ASM support");
+	static assert(0);
+}
+
diff -r a4b91ec616fa -r 7ee2442b6bf4 run/a/asm_punpcklbw_01_A.d
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/run/a/asm_punpcklbw_01_A.d	Wed May 24 16:24:27 2006 +0000
@@ -0,0 +1,86 @@
+// $HeadURL$
+// $Date$
+// $Author$
+
+module dstress.run.a.asm_punpcklbw_01_A;
+
+version(D_InlineAsm_X86){
+	version = runTest;
+}else version(D_InlineAsm_X86_64){
+	version = runTest;
+}
+
+version(runTest){
+	import addon.cpuinfo;
+
+	int main(){
+		haveSSE2!()();
+
+		const byte[16] A = [8, 9, 10, 11, 12, 13, 14, 15, 0, 1, 2, 3, 4, 5, 6, 7];
+		const byte[16] B = [-8, -9, -10, -11, -12, -13, -14, -15, 0, -1, -2, -3, -4, -5, -6, -7];
+
+		byte[16] c;
+
+		asm{
+			movdqu XMM0, A;
+			movdqu XMM1, B;
+			punpcklbw XMM0, XMM1;
+			movdqu c, XMM0;
+		}
+
+		if(c[0] != 0){
+			assert(0);
+		}
+		if(c[1] != 0){
+			assert(0);
+		}
+		if(c[2] != -1){
+			assert(0);
+		}
+		if(c[3] != 1){
+			assert(0);
+		}
+		if(c[4] != -2){
+			assert(0);
+		}
+		if(c[5] != 2){
+			assert(0);
+		}
+		if(c[6] != -3){
+			assert(0);
+		}
+		if(c[7] != 3){
+			assert(0);
+		}
+		if(c[8] != -4){
+			assert(0);
+		}
+		if(c[9] != 4){
+			assert(0);
+		}
+		if(c[10] != -5){
+			assert(0);
+		}
+		if(c[11] != 5){
+			assert(0);
+		}
+		if(c[12] != -6){
+			assert(0);
+		}
+		if(c[13] != 6){
+			assert(0);
+		}
+		if(c[14] != 7){
+			assert(0);
+		}
+		if(c[15] != -7){
+			assert(0);
+		}
+
+		return 0;
+	}
+}else{
+	pragma(msg, "DSTRESS{XFAIL}: no inline ASM support");
+	static assert(0);
+}
+
diff -r a4b91ec616fa -r 7ee2442b6bf4 run/a/asm_punpckldq_01_A.d
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/run/a/asm_punpckldq_01_A.d	Wed May 24 16:24:27 2006 +0000
@@ -0,0 +1,50 @@
+// $HeadURL$
+// $Date$
+// $Author$
+
+module dstress.run.a.asm_punpckldq_01_A;
+
+version(D_InlineAsm_X86){
+	version = runTest;
+}else version(D_InlineAsm_X86_64){
+	version = runTest;
+}
+
+version(runTest){
+	import addon.cpuinfo;
+
+	int main(){
+		haveSSE2!()();
+
+		const int[4] A = [2, 3, 0, 1];
+		const int[4] B = [-2, -3, 0, -1];
+
+		int[4] c;
+
+		asm{
+			movdqu XMM0, A;
+			movdqu XMM1, B;
+			punpckldq XMM0, XMM1;
+			movdqu c, XMM0;
+		}
+
+		if(c[0] != 0){
+			assert(0);
+		}
+		if(c[1] != 0){
+			assert(0);
+		}
+		if(c[2] != -1){
+			assert(0);
+		}
+		if(c[3] != 1){
+			assert(0);
+		}
+
+		return 0;
+	}
+}else{
+	pragma(msg, "DSTRESS{XFAIL}: no inline ASM support");
+	static assert(0);
+}
+
diff -r a4b91ec616fa -r 7ee2442b6bf4 run/a/asm_punpcklqdq_01_A.d
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/run/a/asm_punpcklqdq_01_A.d	Wed May 24 16:24:27 2006 +0000
@@ -0,0 +1,44 @@
+// $HeadURL$
+// $Date$
+// $Author$
+
+module dstress.run.a.asm_punpcklqdq_01_A;
+
+version(D_InlineAsm_X86){
+	version = runTest;
+}else version(D_InlineAsm_X86_64){
+	version = runTest;
+}
+
+version(runTest){
+	import addon.cpuinfo;
+
+	int main(){
+		haveSSE2!()();
+
+		const long[2] A = [2, 1];
+		const long[2] B = [-2, -1];
+
+		long[2] c;
+
+		asm{
+			movdqu XMM0, A;
+			movdqu XMM1, B;
+			punpcklqdq XMM0, XMM1;
+			movdqu c, XMM0;
+		}
+
+		if(c[0] != -1){
+			assert(0);
+		}
+		if(c[1] != 1){
+			assert(0);
+		}
+
+		return 0;
+	}
+}else{
+	pragma(msg, "DSTRESS{XFAIL}: no inline ASM support");
+	static assert(0);
+}
+
diff -r a4b91ec616fa -r 7ee2442b6bf4 run/a/asm_punpcklwd_01_A.d
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/run/a/asm_punpcklwd_01_A.d	Wed May 24 16:24:27 2006 +0000
@@ -0,0 +1,62 @@
+// $HeadURL$
+// $Date$
+// $Author$
+
+module dstress.run.a.asm_punpcklwd_01_A;
+
+version(D_InlineAsm_X86){
+	version = runTest;
+}else version(D_InlineAsm_X86_64){
+	version = runTest;
+}
+
+version(runTest){
+	import addon.cpuinfo;
+
+	int main(){
+		haveSSE2!()();
+
+		const short[8] A = [4, 5, 6, 7, 0, 1, 2, 3, 4];
+		const short[8] B = [-4, -5, -6, -7, 0, -1, -2, -3];
+
+		short[8] c;
+
+		asm{
+			movdqu XMM0, A;
+			movdqu XMM1, B;
+			punpcklwd XMM0, XMM1;
+			movdqu c, XMM0;
+		}
+
+		if(c[0] != 0){
+			assert(0);
+		}
+		if(c[1] != 0){
+			assert(0);
+		}
+		if(c[2] != -1){
+			assert(0);
+		}
+		if(c[3] != 1){
+			assert(0);
+		}
+		if(c[4] != -2){
+			assert(0);
+		}
+		if(c[5] != 2){
+			assert(0);
+		}
+		if(c[6] != -3){
+			assert(0);
+		}
+		if(c[7] != 3){
+			assert(0);
+		}
+
+		return 0;
+	}
+}else{
+	pragma(msg, "DSTRESS{XFAIL}: no inline ASM support");
+	static assert(0);
+}
+
diff -r a4b91ec616fa -r 7ee2442b6bf4 run/a/asm_push_01_A.d
--- a/run/a/asm_push_01_A.d	Wed May 24 16:24:07 2006 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,34 +0,0 @@
-// $HeadURL$
-// $Date$
-// $Author$
-
-module dstress.run.a.asm_push_01_A;
-
-int main(){
-	version(D_InlineAsm){
-		ushort a= 0x12_AB;
-		ushort b= 0x00_00;
-		size_t p1, p2, p3;
-		
-		static if(size_t.sizeof==4){
-			asm{
-				mov p1, ESP;
-				push a;
-				mov p2, ESP;
-				pop b;
-				mov p3, ESP;
-			}
-		}else{
-			static assert(0);
-		}
-		
-		assert(p1==p3);
-		assert(p1-2==p2);
-		assert(b==0x12_AB);
-		
-		return 0;
-	}else{
-		pragma(msg, "no Inline asm support");
-		static assert(0);
-	}
-}
\ No newline at end of file
diff -r a4b91ec616fa -r 7ee2442b6bf4 run/a/asm_push_01_B.d
--- a/run/a/asm_push_01_B.d	Wed May 24 16:24:07 2006 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,31 +0,0 @@
-// $HeadURL$
-// $Date$
-// $Author$
-
-module dstress.run.a.asm_push_01_B;
-
-int main(){
-	version(D_InlineAsm){
-		static if(size_t.sizeof==4){
-			uint a= 0x12_AB_34_CD;
-			uint b= 0x00_00_00_00;
-			size_t p1, p2, p3;
-		
-			asm{
-				mov p1, ESP;
-				push a;
-				mov p2, ESP;
-				pop b;
-				mov p3, ESP;
-			}
-		
-			assert(p1==p3);
-			assert(p1-4==p2);
-			assert(b==0x12_AB_34_CD);
-		}
-		return 0;
-	}else{
-		pragma(msg, "no Inline asm support");
-		static assert(0);
-	}
-}
\ No newline at end of file
diff -r a4b91ec616fa -r 7ee2442b6bf4 run/a/asm_push_02_A.d
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/run/a/asm_push_02_A.d	Wed May 24 16:24:27 2006 +0000
@@ -0,0 +1,46 @@
+// $HeadURL$
+// $Date$
+// $Author$
+
+module dstress.run.a.asm_pop_02_A;
+
+version(D_InlineAsm_X86){
+	version = runTest;
+}else version(D_InlineAsm_X86_64){
+	version = runTest;
+}
+
+version(runTest){
+	int main(){
+		size_t a;
+		size_t p1, p2, p3;
+		
+		static if(size_t.sizeof == 4){
+			asm{
+				mov p1, ESP;
+				push 0x12;
+				mov p2, ESP;
+				pop a;
+				mov p3, ESP;
+			}
+		}else{
+			pragma(msg, "DSTRESS{ERROR}: unhandled size of void pointer");
+			static assert(0);
+		}
+		
+		if(p1 != p3){
+			assert(0);
+		}
+		if(p1 - size_t.sizeof != p2){
+			assert(0);
+		}
+		if(a != 0x12){
+			assert(0);
+		}
+		
+		return 0;
+	}
+}else{
+	pragma(msg, "DSTRESS{XFAIL}: no inline ASM support");
+	static assert(0);
+}
diff -r a4b91ec616fa -r 7ee2442b6bf4 run/a/asm_pusha_01.d
--- a/run/a/asm_pusha_01.d	Wed May 24 16:24:07 2006 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,51 +0,0 @@
-// $HeadURL$
-// $Date$
-// $Author$
-
-module dstress.run.a.asm_pusha_01;
-
-int main(){
-	version(D_InlineAsm){
-		static if(size_t.sizeof <= 4){
-			ushort a1, b1, c1, d1;
-			ushort a2, b2, c2, d2;
-			ushort a3, b3, c3, d3;
-			
-			asm{
-				mov a1, AX;
-				mov b1, BX;
-				mov c1, CX;
-				mov d1, DX;
-				pusha;
-				mov EAX, 1;
-				mov EBX, 2;
-				mov ECX, 3;
-				mov EDX, 4;
-				mov a2, AX;
-				mov b2, BX;
-				mov c2, CX;
-				mov d2, DX;
-				popa;
-				mov a3, AX;
-				mov b3, BX;
-				mov c3, CX;
-				mov d3, DX;				
-			}
-			
-			assert(a1 == a3);
-			assert(b1 == b3);
-			assert(c1 == c3);
-			assert(d1 == d3);
-			
-			assert(a2 == 1);
-			assert(b2 == 2);
-			assert(c2 == 3);
-			assert(d2 == 4);
-		}
-		
-		return 0;
-	}else{
-		pragma(msg, "no Inline asm support");
-		static assert(0);
-	}
-}
\ No newline at end of file
diff -r a4b91ec616fa -r 7ee2442b6bf4 run/a/asm_pushad_01.d
--- a/run/a/asm_pushad_01.d	Wed May 24 16:24:07 2006 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,72 +0,0 @@
-// $HeadURL$
-// $Date$
-// $Author$
-
-module dstress.run.a.asm_pushad_01;
-
-int main(){
-	version(D_InlineAsm){
-		static if(size_t.sizeof==4){
-			uint a_A, a_B, a_C, a_D, a_BP, a_SP, a_SI, a_DI;
-			uint b_A, b_B, b_C, b_D, b_BP, b_SP, b_SI, b_DI;
-			uint c_A, c_B, c_C, c_D, c_BP, c_SP, c_SI, c_DI;
-			uint x = 0x12_AB_CD_34;
-			asm{
-				mov a_A, EAX;
-				mov a_B, EBX;
-				mov a_C, ECX;
-				mov a_D, EDX;
-				mov a_BP, EBP;
-				mov a_SP, ESP;
-				mov a_SI, ESI;
-				mov a_DI, EDI;
-				pushad;
-				mov EAX, x;
-				mov EBX, x;
-				mov ECX, x;
-				mov EDX, x;
-				mov ESI, x;
-				mov EDI, x;
-				mov b_A, EAX;
-				mov b_B, EBX;
-				mov b_C, ECX;
-				mov b_D, EDX;
-				mov b_BP, EBP;
-				mov b_SP, ESP;
-				mov b_SI, ESI;
-				mov b_DI, EDI;
-				popad;
-				mov c_A, EAX;
-				mov c_B, EBX;
-				mov c_C, ECX;
-				mov c_D, EDX;
-				mov c_BP, EBP;
-				mov c_SP, ESP;
-				mov c_SI, ESI;
-				mov c_DI, EDI;			
-			}
-			
-			assert(a_A == c_A);
-			assert(b_A == x);
-			
-			assert(a_B == c_B);
-			assert(b_B == x);
-			
-			assert(a_C == c_C);
-			assert(b_C == x);
-			
-			assert(a_D == c_D);
-			assert(b_D == x);
-			
-			assert(a_SI == c_SI);
-			assert(b_SI == x);
-						
-			assert(a_SI == c_SI);
-			assert(b_SI == x);
-		}
-		return 0;
-	}else{
-		pragma(msg, "no Inline asm support");
-		static assert(0);
-	}
-}
diff -r a4b91ec616fa -r 7ee2442b6bf4 run/a/asm_pxor_01_A.d
--- a/run/a/asm_pxor_01_A.d	Wed May 24 16:24:07 2006 +0000
+++ b/run/a/asm_pxor_01_A.d	Wed May 24 16:24:27 2006 +0000
@@ -4,8 +4,18 @@
 
 module dstress.run.a.asm_pxor_01_A;
 
-int main(){
-	version(D_InlineAsm){
+version(D_InlineAsm_X86){
+	version = runTest;
+}else version(D_InlineAsm_X86_64){
+	version = runTest;
+}
+
+version(runTest){
+	import addon.cpuinfo;
+
+	int main(){
+		haveSSE2!()();
+
 		ulong a = 0xFF01_00FF_0001_0000;
 		ulong b = 0xFF00_00FF_0002_0000;
 		ulong c = 2;
@@ -16,11 +26,13 @@
 			movq c, MM0;
 		}
 				
-		assert(c==0x0001_0000_0003_0000);
+		if(c != 0x0001_0000_0003_0000){
+			assert(0);
+		}
 
 		return 0;
-	}else{
-		pragma(msg, "no Inline asm support");
-		static assert(0);
 	}
-}
\ No newline at end of file
+}else{
+	pragma(msg, "DSTRESS{XFAIL}: no inline ASM support");
+	static assert(0);
+}
diff -r a4b91ec616fa -r 7ee2442b6bf4 run/a/asm_pxor_02_A.d
--- a/run/a/asm_pxor_02_A.d	Wed May 24 16:24:07 2006 +0000
+++ b/run/a/asm_pxor_02_A.d	Wed May 24 16:24:27 2006 +0000
@@ -4,38 +4,48 @@
 
 module dstress.run.a.asm_pxor_02_A;
 
-int main(){
-	version(D_InlineAsm_X86){
+version(D_InlineAsm_X86){
+	version = runTest;
+}else version(D_InlineAsm_X86_64){
+	version = runTest;
+}
+
+version(runTest){
+	import addon.cpuinfo;
+	
+	int main(){
+		haveSSE2!()();
+
 		static ushort[8] A = [0x1200, 0x0120, 0x0012, 0x2001, 0x0008, 0xFFFF, 0x0000, 0x1111];
 		static ushort[8] B = [0x2100, 0x2100, 0x2100, 0x2100, 0x2100, 0x0F00, 0x0102, 0x2222];
 		static ushort[8] C = [0x3300, 0x2020, 0x2112, 0x0101, 0x2108, 0xF0FF, 0x0102, 0x3333];
 
-		ushort[8] a = A;
-		ushort[8] b = B;
+		ushort[8] d;
+		ushort[8] e;
 		
 		asm{
 			movdqu XMM0, A;
 			movdqu XMM1, B;
 			pxor XMM1, XMM0;
-			movdqu a, XMM0;
-			movdqu b, XMM1;
+			movdqu d, XMM0;
+			movdqu e, XMM1;
 		}
 
 
 		foreach(size_t i, ushort s; A){
-			if(s != a[i]){
+			if(s != d[i]){
 				assert(0);
 			}
 		}
 		foreach(size_t i, ushort s; C){
-			if(s != b[i]){
+			if(s != e[i]){
 				assert(0);
 			}
 		}
 		
 		return 0;
-	}else{
-		pragma(msg, "no Inline asm support");
-		static assert(0);
 	}
+}else{
+	pragma(msg, "DSTRESS{XFAIL}: no inline ASM support");
+	static assert(0);
 }
diff -r a4b91ec616fa -r 7ee2442b6bf4 run/a/asm_pxor_02_B.d
--- a/run/a/asm_pxor_02_B.d	Wed May 24 16:24:07 2006 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,33 +0,0 @@
-// $HeadURL$
-// $Date$
-// $Author$
-
-module dstress.run.a.asm_pxor_02_B;
-
-int main(){
-	version(D_InlineAsm_X86){
-		static ushort[8] A = [0x1200, 0x0120, 0x0012, 0x2001, 0x0008, 0xFFFF, 0x0000, 0x1111];
-		static ushort[8] B = [0x2100, 0x2100, 0x2100, 0x2100, 0x2100, 0x0F00, 0x0102, 0x2222];
-		static ushort[8] C = [0x3300, 0x2020, 0x2112, 0x0101, 0x2108, 0xF0FF, 0x0102, 0x3333];
-
-		ushort[8] a;
-		
-		asm{
-			movdqu XMM0, A;
-			por XMM0, B;
-			movdqu a, XMM0;
-		}
-
-
-		foreach(size_t i, ushort s; C){
-			if(s != a[i]){
-				assert(0);
-			}
-		}
-		
-		return 0;
-	}else{
-		pragma(msg, "no Inline asm support");
-		static assert(0);
-	}
-}