# HG changeset patch
# User thomask
# Date 1148328924 0
# Node ID 26f680ab52cd5a5eb6c877a21b37ca133577aa82
# Parent  cddb4604d6d7936c598050d0fbb951ba2f29bd1d
inline ASM review

diff -r cddb4604d6d7 -r 26f680ab52cd run/a/asm_orps_01_A.d
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/run/a/asm_orps_01_A.d	Mon May 22 20:15:24 2006 +0000
@@ -0,0 +1,48 @@
+// $HeadURL$
+// $Date$
+// $Author$
+
+module dstress.run.a.asm_orps_01_A;
+
+version(D_InlineAsm_X86){
+	version = runTest;
+}else version(D_InlineAsm_X86_64){
+	version = runTest;
+}
+
+version(runTest){
+	import addon.cpuinfo;
+	
+	int main(){
+		haveSSE!()();
+
+		static float[4] A = [5.0f, 10.0f, 1.0f, 17.0f];
+		static float[4] B = [6.0f, 9.0f, -2.0f, 20.0f];
+		float[4] c;
+				
+		asm{
+			movups XMM0, A;
+			movups XMM1, B;
+			orpd XMM0, XMM1;
+			movups c, XMM0;
+		}
+
+		if(c[0] != 7.0f){
+			assert(0);
+		}
+		if(c[1] != 11.0f){
+			assert(0);
+		}
+		if(c[2] != -float.infinity){
+			assert(0);
+		}
+		if(c[3] != 21.0f){
+			assert(0);
+		}
+
+		return 0;
+	}
+}else{
+	pragma(msg, "DSTRESS{XFAIL}: no inline ASM support");
+	static assert(0);
+}
diff -r cddb4604d6d7 -r 26f680ab52cd run/a/asm_packssdw_01_A.d
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/run/a/asm_packssdw_01_A.d	Mon May 22 20:15:24 2006 +0000
@@ -0,0 +1,58 @@
+// $HeadURL$
+// $Date$
+// $Author$
+
+module dstress.run.a.asm_packssdw_01_A;
+
+version(D_InlineAsm_X86){
+	version = runTest;
+}else version(D_InlineAsm_X86_64){
+	version = runTest;
+}
+
+version(runTest){
+	import addon.cpuinfo;
+	
+	int main(){
+		haveSSE2!()();
+
+		static int[4] A = [1, -2, 3, -4];
+		static int[4] B = [5, -6, 7, -8];
+		short[8] c;
+				
+		asm{
+			movdqu XMM0, A;
+			movdqu XMM1, B;
+			packssdw XMM0, XMM1;
+			movdqu c, XMM0;
+		}
+		if(c[0] != 1){
+			assert(0);
+		}
+		if(c[1] != -2){
+			assert(0);
+		}
+		if(c[2] != 3){
+			assert(0);
+		}
+		if(c[3] != -4){
+			assert(0);
+		}
+		if(c[4] != 5){
+			assert(0);
+		}
+		if(c[5] != -6){
+			assert(0);
+		}
+		if(c[6] != 7){
+			assert(0);
+		}
+		if(c[7] != -8){
+			assert(0);
+		}
+		return 0;
+	}
+}else{
+	pragma(msg, "DSTRESS{XFAIL}: no inline ASM support");
+	static assert(0);
+}
diff -r cddb4604d6d7 -r 26f680ab52cd run/a/asm_packsswb_01_A.d
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/run/a/asm_packsswb_01_A.d	Mon May 22 20:15:24 2006 +0000
@@ -0,0 +1,83 @@
+// $HeadURL$
+// $Date$
+// $Author$
+
+module dstress.run.a.asm_packsswb_01_A;
+
+version(D_InlineAsm_X86){
+	version = runTest;
+}else version(D_InlineAsm_X86_64){
+	version = runTest;
+}
+
+version(runTest){
+	import addon.cpuinfo;
+	
+	int main(){
+		haveSSE2!()();
+
+		static short[8] A = [1, -2, 3, -4, 5, -6, 7, -8];
+		static short[8] B = [9, 8, -7, 6, -5, 4, -3, 2];
+		byte[16] c;
+				
+		asm{
+			movdqu XMM0, A;
+			movdqu XMM1, B;
+			packsswb XMM0, XMM1;
+			movdqu c, XMM0;
+		}
+
+		if(c[0] != 1){
+			assert(0);
+		}
+		if(c[1] != -2){
+			assert(0);
+		}
+		if(c[2] != 3){
+			assert(0);
+		}
+		if(c[3] != -4){
+			assert(0);
+		}
+		if(c[4] != 5){
+			assert(0);
+		}
+		if(c[5] != -6){
+			assert(0);
+		}
+		if(c[6] != 7){
+			assert(0);
+		}
+		if(c[7] != -8){
+			assert(0);
+		}
+		if(c[8] != 9){
+			assert(0);
+		}
+		if(c[9] != 8){
+			assert(0);
+		}
+		if(c[10] != -7){
+			assert(0);
+		}
+		if(c[11] != 6){
+			assert(0);
+		}
+		if(c[12] != -5){
+			assert(0);
+		}
+		if(c[13] != 4){
+			assert(0);
+		}
+		if(c[14] != -3){
+			assert(0);
+		}
+		if(c[15] != 2){
+			assert(0);
+		}
+		return 0;
+	}
+}else{
+	pragma(msg, "DSTRESS{XFAIL}: no inline ASM support");
+	static assert(0);
+}
diff -r cddb4604d6d7 -r 26f680ab52cd run/a/asm_packuswb_01_A.d
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/run/a/asm_packuswb_01_A.d	Mon May 22 20:15:24 2006 +0000
@@ -0,0 +1,83 @@
+// $HeadURL$
+// $Date$
+// $Author$
+
+module dstress.run.a.asm_packuswb_01_A;
+
+version(D_InlineAsm_X86){
+	version = runTest;
+}else version(D_InlineAsm_X86_64){
+	version = runTest;
+}
+
+version(runTest){
+	import addon.cpuinfo;
+	
+	int main(){
+		haveSSE2!()();
+
+		static short[8] A = [1, -2, 3, -4, 5, -6, 7, -8];
+		static short[8] B = [9, 8, -7, 6, -5, 4, -3, 2];
+		byte[16] c;
+				
+		asm{
+			movdqu XMM0, A;
+			movdqu XMM1, B;
+			packuswb XMM0, XMM1;
+			movdqu c, XMM0;
+		}
+
+		if(c[0] != 1){
+			assert(0);
+		}
+		if(c[1] != 0){
+			assert(0);
+		}
+		if(c[2] != 3){
+			assert(0);
+		}
+		if(c[3] != 0){
+			assert(0);
+		}
+		if(c[4] != 5){
+			assert(0);
+		}
+		if(c[5] != 0){
+			assert(0);
+		}
+		if(c[6] != 7){
+			assert(0);
+		}
+		if(c[7] != 0){
+			assert(0);
+		}
+		if(c[8] != 9){
+			assert(0);
+		}
+		if(c[9] != 8){
+			assert(0);
+		}
+		if(c[10] != 0){
+			assert(0);
+		}
+		if(c[11] != 6){
+			assert(0);
+		}
+		if(c[12] != 0){
+			assert(0);
+		}
+		if(c[13] != 4){
+			assert(0);
+		}
+		if(c[14] != 0){
+			assert(0);
+		}
+		if(c[15] != 2){
+			assert(0);
+		}
+		return 0;
+	}
+}else{
+	pragma(msg, "DSTRESS{XFAIL}: no inline ASM support");
+	static assert(0);
+}
diff -r cddb4604d6d7 -r 26f680ab52cd run/a/asm_paddb_01_A.d
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/run/a/asm_paddb_01_A.d	Mon May 22 20:15:24 2006 +0000
@@ -0,0 +1,83 @@
+// $HeadURL$
+// $Date$
+// $Author$
+
+module dstress.run.a.asm_paddb_01_A;
+
+version(D_InlineAsm_X86){
+	version = runTest;
+}else version(D_InlineAsm_X86_64){
+	version = runTest;
+}
+
+version(runTest){
+	import addon.cpuinfo;
+	
+	int main(){
+		haveSSE2!()();
+
+		static byte[16] A = [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16];
+		static byte[16] B = [-8, -7, -6, -5, -4, -3, -2, -1, 0, 1, 2, 3, 4, 5, 6, 7];
+		byte[16] c;
+				
+		asm{
+			movdqu XMM0, A;
+			movdqu XMM1, B;
+			paddb XMM0, XMM1;
+			movdqu c, XMM0;
+		}
+
+		if(c[0] != -7){
+			assert(0);
+		}
+		if(c[1] != -5){
+			assert(0);
+		}
+		if(c[2] != -3){
+			assert(0);
+		}
+		if(c[3] != -1){
+			assert(0);
+		}
+		if(c[4] != 1){
+			assert(0);
+		}
+		if(c[5] != 3){
+			assert(0);
+		}
+		if(c[6] != 5){
+			assert(0);
+		}
+		if(c[7] != 7){
+			assert(0);
+		}
+		if(c[8] != 9){
+			assert(0);
+		}
+		if(c[9] != 11){
+			assert(0);
+		}
+		if(c[10] != 13){
+			assert(0);
+		}
+		if(c[11] != 15){
+			assert(0);
+		}
+		if(c[12] != 17){
+			assert(0);
+		}
+		if(c[13] != 19){
+			assert(0);
+		}
+		if(c[14] != 21){
+			assert(0);
+		}
+		if(c[15] != 23){
+			assert(0);
+		}
+		return 0;
+	}
+}else{
+	pragma(msg, "DSTRESS{XFAIL}: no inline ASM support");
+	static assert(0);
+}
diff -r cddb4604d6d7 -r 26f680ab52cd run/a/asm_paddd_01_A.d
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/run/a/asm_paddd_01_A.d	Mon May 22 20:15:24 2006 +0000
@@ -0,0 +1,47 @@
+// $HeadURL$
+// $Date$
+// $Author$
+
+module dstress.run.a.asm_paddd_01_A;
+
+version(D_InlineAsm_X86){
+	version = runTest;
+}else version(D_InlineAsm_X86_64){
+	version = runTest;
+}
+
+version(runTest){
+	import addon.cpuinfo;
+	
+	int main(){
+		haveSSE2!()();
+
+		static int[4] A = [1, 2, 3, 4];
+		static int[4] B = [int.max-2, int.min, 0, -6];
+		int[4] c;
+				
+		asm{
+			movdqu XMM0, A;
+			movdqu XMM1, B;
+			paddd XMM0, XMM1;
+			movdqu c, XMM0;
+		}
+
+		if(c[0] != int.max - 1){
+			assert(0);
+		}
+		if(c[1] != int.min + 2){
+			assert(0);
+		}
+		if(c[2] != 3){
+			assert(0);
+		}
+		if(c[3] != -2){
+			assert(0);
+		}
+		return 0;
+	}
+}else{
+	pragma(msg, "DSTRESS{XFAIL}: no inline ASM support");
+	static assert(0);
+}
diff -r cddb4604d6d7 -r 26f680ab52cd run/a/asm_paddq_01_A.d
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/run/a/asm_paddq_01_A.d	Mon May 22 20:15:24 2006 +0000
@@ -0,0 +1,41 @@
+// $HeadURL$
+// $Date$
+// $Author$
+
+module dstress.run.a.asm_paddq_01_A;
+
+version(D_InlineAsm_X86){
+	version = runTest;
+}else version(D_InlineAsm_X86_64){
+	version = runTest;
+}
+
+version(runTest){
+	import addon.cpuinfo;
+	
+	int main(){
+		haveSSE2!()();
+
+		static long[2] A = [-1, -2];
+		static long[2] B = [2, long.max];
+		long[2] c;
+				
+		asm{
+			movdqu XMM0, A;
+			movdqu XMM1, B;
+			paddq XMM0, XMM1;
+			movdqu c, XMM0;
+		}
+
+		if(c[0] != 1){
+			assert(0);
+		}
+		if(c[1] != long.max - 2){
+			assert(0);
+		}
+		return 0;
+	}
+}else{
+	pragma(msg, "DSTRESS{XFAIL}: no inline ASM support");
+	static assert(0);
+}
diff -r cddb4604d6d7 -r 26f680ab52cd run/a/asm_paddsb_01_A.d
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/run/a/asm_paddsb_01_A.d	Mon May 22 20:15:24 2006 +0000
@@ -0,0 +1,83 @@
+// $HeadURL$
+// $Date$
+// $Author$
+
+module dstress.run.a.asm_paddsb_01_A;
+
+version(D_InlineAsm_X86){
+	version = runTest;
+}else version(D_InlineAsm_X86_64){
+	version = runTest;
+}
+
+version(runTest){
+	import addon.cpuinfo;
+	
+	int main(){
+		haveSSE2!()();
+
+		static byte[16] A = [1, byte.min, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16];
+		static byte[16] B = [byte.max, -7, -6, -5, -4, -3, -2, -1, 0, 1, 2, 3, 4, 5, 6, 7];
+		byte[16] c;
+				
+		asm{
+			movdqu XMM0, A;
+			movdqu XMM1, B;
+			paddsb XMM0, XMM1;
+			movdqu c, XMM0;
+		}
+
+		if(c[0] != byte.max){
+			assert(0);
+		}
+		if(c[1] != byte.min){
+			assert(0);
+		}
+		if(c[2] != -3){
+			assert(0);
+		}
+		if(c[3] != -1){
+			assert(0);
+		}
+		if(c[4] != 1){
+			assert(0);
+		}
+		if(c[5] != 3){
+			assert(0);
+		}
+		if(c[6] != 5){
+			assert(0);
+		}
+		if(c[7] != 7){
+			assert(0);
+		}
+		if(c[8] != 9){
+			assert(0);
+		}
+		if(c[9] != 11){
+			assert(0);
+		}
+		if(c[10] != 13){
+			assert(0);
+		}
+		if(c[11] != 15){
+			assert(0);
+		}
+		if(c[12] != 17){
+			assert(0);
+		}
+		if(c[13] != 19){
+			assert(0);
+		}
+		if(c[14] != 21){
+			assert(0);
+		}
+		if(c[15] != 23){
+			assert(0);
+		}
+		return 0;
+	}
+}else{
+	pragma(msg, "DSTRESS{XFAIL}: no inline ASM support");
+	static assert(0);
+}
diff -r cddb4604d6d7 -r 26f680ab52cd run/a/asm_paddsw_01_A.d
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/run/a/asm_paddsw_01_A.d	Mon May 22 20:15:24 2006 +0000
@@ -0,0 +1,59 @@
+// $HeadURL$
+// $Date$
+// $Author$
+
+module dstress.run.a.asm_paddsw_01_A;
+
+version(D_InlineAsm_X86){
+	version = runTest;
+}else version(D_InlineAsm_X86_64){
+	version = runTest;
+}
+
+version(runTest){
+	import addon.cpuinfo;
+	
+	int main(){
+		haveSSE2!()();
+
+		static short[8] A = [1, short.min, 3, 4, 5, 6, 7, 8];
+		static short[8] B = [short.max, -8, -7, -6, -5, -4, -3, -2];
+		short[8] c;
+				
+		asm{
+			movdqu XMM0, A;
+			movdqu XMM1, B;
+			paddsw XMM0, XMM1;
+			movdqu c, XMM0;
+		}
+
+		if(c[0] != short.max){
+			assert(0);
+		}
+		if(c[1] != short.min){
+			assert(0);
+		}
+		if(c[2] != -4){
+			assert(0);
+		}
+		if(c[3] != -2){
+			assert(0);
+		}
+		if(c[4] != 0){
+			assert(0);
+		}
+		if(c[5] != 2){
+			assert(0);
+		}
+		if(c[6] != 4){
+			assert(0);
+		}
+		if(c[7] != 6){
+			assert(0);
+		}
+		return 0;
+	}
+}else{
+	pragma(msg, "DSTRESS{XFAIL}: no inline ASM support");
+	static assert(0);
+}
diff -r cddb4604d6d7 -r 26f680ab52cd run/a/asm_paddusb_01_A.d
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/run/a/asm_paddusb_01_A.d	Mon May 22 20:15:24 2006 +0000
@@ -0,0 +1,83 @@
+// $HeadURL$
+// $Date$
+// $Author$
+
+module dstress.run.a.asm_paddusb_01_A;
+
+version(D_InlineAsm_X86){
+	version = runTest;
+}else version(D_InlineAsm_X86_64){
+	version = runTest;
+}
+
+version(runTest){
+	import addon.cpuinfo;
+	
+	int main(){
+		haveSSE2!()();
+
+		static ubyte[16] A = [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16];
+		static ubyte[16] B = [ubyte.max, 7, 6, 5, 4, 3, 2, 1, 0, 1, 2, 3, 4, 5, 6, 7];
+		ubyte[16] c;
+				
+		asm{
+			movdqu XMM0, A;
+			movdqu XMM1, B;
+			paddusb XMM0, XMM1;
+			movdqu c, XMM0;
+		}
+
+		if(c[0] != ubyte.max){
+			assert(0);
+		}
+		if(c[1] != 9){
+			assert(0);
+		}
+		if(c[2] != 9){
+			assert(0);
+		}
+		if(c[3] != 9){
+			assert(0);
+		}
+		if(c[4] != 9){
+			assert(0);
+		}
+		if(c[5] != 9){
+			assert(0);
+		}
+		if(c[6] != 9){
+			assert(0);
+		}
+		if(c[7] != 9){
+			assert(0);
+		}
+		if(c[8] != 9){
+			assert(0);
+		}
+		if(c[9] != 11){
+			assert(0);
+		}
+		if(c[10] != 13){
+			assert(0);
+		}
+		if(c[11] != 15){
+			assert(0);
+		}
+		if(c[12] != 17){
+			assert(0);
+		}
+		if(c[13] != 19){
+			assert(0);
+		}
+		if(c[14] != 21){
+			assert(0);
+		}
+		if(c[15] != 23){
+			assert(0);
+		}
+		return 0;
+	}
+}else{
+	pragma(msg, "DSTRESS{XFAIL}: no inline ASM support");
+	static assert(0);
+}
diff -r cddb4604d6d7 -r 26f680ab52cd run/a/asm_paddusw_01_A.d
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/run/a/asm_paddusw_01_A.d	Mon May 22 20:15:24 2006 +0000
@@ -0,0 +1,59 @@
+// $HeadURL$
+// $Date$
+// $Author$
+
+module dstress.run.a.asm_paddusw_01_A;
+
+version(D_InlineAsm_X86){
+	version = runTest;
+}else version(D_InlineAsm_X86_64){
+	version = runTest;
+}
+
+version(runTest){
+	import addon.cpuinfo;
+	
+	int main(){
+		haveSSE2!()();
+
+		static ushort[8] A = [1, 0, 3, 4, 5, 6, 7, 8];
+		static ushort[8] B = [ushort.max, 8, 7, 6, 5, 4, 3, 2];
+		ushort[8] c;
+				
+		asm{
+			movdqu XMM0, A;
+			movdqu XMM1, B;
+			paddusw XMM0, XMM1;
+			movdqu c, XMM0;
+		}
+
+		if(c[0] != ushort.max){
+			assert(0);
+		}
+		if(c[1] != 8){
+			assert(0);
+		}
+		if(c[2] != 10){
+			assert(0);
+		}
+		if(c[3] != 10){
+			assert(0);
+		}
+		if(c[4] != 10){
+			assert(0);
+		}
+		if(c[5] != 10){
+			assert(0);
+		}
+		if(c[6] != 10){
+			assert(0);
+		}
+		if(c[7] != 10){
+			assert(0);
+		}
+		return 0;
+	}
+}else{
+	pragma(msg, "DSTRESS{XFAIL}: no inline ASM support");
+	static assert(0);
+}
diff -r cddb4604d6d7 -r 26f680ab52cd run/a/asm_paddw_01_A.d
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/run/a/asm_paddw_01_A.d	Mon May 22 20:15:24 2006 +0000
@@ -0,0 +1,59 @@
+// $HeadURL$
+// $Date$
+// $Author$
+
+module dstress.run.a.asm_paddw_01_A;
+
+version(D_InlineAsm_X86){
+	version = runTest;
+}else version(D_InlineAsm_X86_64){
+	version = runTest;
+}
+
+version(runTest){
+	import addon.cpuinfo;
+	
+	int main(){
+		haveSSE2!()();
+
+		static short[8] A = [1, 2, 3, 4, 5, 6, 7, 8];
+		static short[8] B = [-9, -8, -7, -6, -5, -4, -3, -2];
+		short[8] c;
+				
+		asm{
+			movdqu XMM0, A;
+			movdqu XMM1, B;
+			paddw XMM0, XMM1;
+			movdqu c, XMM0;
+		}
+
+		if(c[0] != -8){
+			assert(0);
+		}
+		if(c[1] != -6){
+			assert(0);
+		}
+		if(c[2] != -4){
+			assert(0);
+		}
+		if(c[3] != -2){
+			assert(0);
+		}
+		if(c[4] != 0){
+			assert(0);
+		}
+		if(c[5] != 2){
+			assert(0);
+		}
+		if(c[6] != 4){
+			assert(0);
+		}
+		if(c[7] != 6){
+			assert(0);
+		}
+		return 0;
+	}
+}else{
+	pragma(msg, "DSTRESS{XFAIL}: no inline ASM support");
+	static assert(0);
+}
diff -r cddb4604d6d7 -r 26f680ab52cd run/a/asm_pand_01_A.d
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/run/a/asm_pand_01_A.d	Mon May 22 20:15:24 2006 +0000
@@ -0,0 +1,65 @@
+// $HeadURL$
+// $Date$
+// $Author$
+
+module dstress.run.a.asm_pand_01_A;
+
+version(D_InlineAsm_X86){
+	version = runTest;
+}else version(D_InlineAsm_X86_64){
+	version = runTest;
+}
+
+version(runTest){
+	import addon.cpuinfo;
+	
+	int main(){
+		haveSSE2!()();
+
+		static ushort[8] A = [
+			0b01101100_01101110, 0b01101001_01101101, 0b01100011_01101011, 0b11100111_01100111,
+			0b11000110_11100110, 0b10001101_10011011, 0b00011011_10011011, 0b01100110_00000000
+		];
+		static ushort[8] B = [
+			0b10000000_11000000, 0b01000000_01100000, 0b00100000_00110000, 0b00010000_00011000,
+			0b00001000_00001100, 0b00000100_00000110, 0b00000010_00000011, 0b11111111_10101010
+		];
+		ushort[8] c;
+				
+		asm{
+			movdqu XMM0, A;
+			movdqu XMM1, B;
+			pand XMM0, XMM1;
+			movdqu c, XMM0;
+		}
+
+		if(c[0] != (A[0] & B[0])){
+			assert(0);
+		}
+		if(c[1] != (A[1] & B[1])){
+			assert(0);
+		}
+		if(c[2] != (A[2] & B[2])){
+			assert(0);
+		}
+		if(c[3] != (A[3] & B[3])){
+			assert(0);
+		}
+		if(c[4] != (A[4] & B[4])){
+			assert(0);
+		}
+		if(c[5] != (A[5] & B[5])){
+			assert(0);
+		}
+		if(c[6] != (A[6] & B[6])){
+			assert(0);
+		}
+		if(c[7] != (A[7] & B[7])){
+			assert(0);
+		}
+		return 0;
+	}
+}else{
+	pragma(msg, "DSTRESS{XFAIL}: no inline ASM support");
+	static assert(0);
+}
diff -r cddb4604d6d7 -r 26f680ab52cd run/a/asm_pandn_01_A.d
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/run/a/asm_pandn_01_A.d	Mon May 22 20:15:24 2006 +0000
@@ -0,0 +1,65 @@
+// $HeadURL$
+// $Date$
+// $Author$
+
+module dstress.run.a.asm_pandn_01_A;
+
+version(D_InlineAsm_X86){
+	version = runTest;
+}else version(D_InlineAsm_X86_64){
+	version = runTest;
+}
+
+version(runTest){
+	import addon.cpuinfo;
+	
+	int main(){
+		haveSSE2!()();
+
+		static ushort[8] A = [
+			0b01101100_01101110, 0b01101001_01101101, 0b01100011_01101011, 0b11100111_01100111,
+			0b11000110_11100110, 0b10001101_10011011, 0b00011011_10011011, 0b01100110_00000000
+		];
+		static ushort[8] B = [
+			0b10000000_11000000, 0b01000000_01100000, 0b00100000_00110000, 0b00010000_00011000,
+			0b00001000_00001100, 0b00000100_00000110, 0b00000010_00000011, 0b11111111_10101010
+		];
+		ushort[8] c;
+				
+		asm{
+			movdqu XMM0, A;
+			movdqu XMM1, B;
+			pandn XMM0, XMM1;
+			movdqu c, XMM0;
+		}
+
+		if(c[0] != ((A[0] ^ 0xFFFF) & B[0])){
+			assert(0);
+		}
+		if(c[1] != ((A[1] ^ 0xFFFF) & B[1])){
+			assert(0);
+		}
+		if(c[2] != ((A[2] ^ 0xFFFF) & B[2])){
+			assert(0);
+		}
+		if(c[3] != ((A[3] ^ 0xFFFF) & B[3])){
+			assert(0);
+		}
+		if(c[4] != ((A[4] ^ 0xFFFF) & B[4])){
+			assert(0);
+		}
+		if(c[5] != ((A[5] ^ 0xFFFF) & B[5])){
+			assert(0);
+		}
+		if(c[6] != ((A[6] ^ 0xFFFF) & B[6])){
+			assert(0);
+		}
+		if(c[7] != ((A[7] ^ 0xFFFF) & B[7])){
+			assert(0);
+		}
+		return 0;
+	}
+}else{
+	pragma(msg, "DSTRESS{XFAIL}: no inline ASM support");
+	static assert(0);
+}
diff -r cddb4604d6d7 -r 26f680ab52cd run/a/asm_pause_01_A.d
--- a/run/a/asm_pause_01_A.d	Mon May 22 20:15:07 2006 +0000
+++ b/run/a/asm_pause_01_A.d	Mon May 22 20:15:24 2006 +0000
@@ -4,8 +4,14 @@
 
 module dstress.run.a.asm_pause_01_A;
 
-int main(){
-	version(D_InlineAsm_X86){
+version(D_InlineAsm_X86){
+	version = runTest;
+}else version(D_InlineAsm_X86_64){
+	version = runTest;
+}
+
+version(runTest){
+	int main(){
 
 		asm{
 			rep;
@@ -13,8 +19,8 @@
 		}
 
 		return 0;
-	}else{
-		pragma(msg, "no Inline asm support");
-		static assert(0);
 	}
+}else{
+	pragma(msg, "DSTRESS{XFAIL}: no inline ASM support");
+	static assert(0);
 }
diff -r cddb4604d6d7 -r 26f680ab52cd run/a/asm_pavgb_01_A.d
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/run/a/asm_pavgb_01_A.d	Mon May 22 20:15:24 2006 +0000
@@ -0,0 +1,43 @@
+// $HeadURL$
+// $Date$
+// $Author$
+
+module dstress.run.a.asm_pavgb_01_A;
+
+version(D_InlineAsm_X86){
+	version = runTest;
+}else version(D_InlineAsm_X86_64){
+	version = runTest;
+}
+
+version(runTest){
+	import addon.cpuinfo;
+	
+	int main(){
+		haveSSE!()();
+
+		const byte[8] A = [1, -2, 3, 4, 5, 6, 7, 8];
+		const byte[8] B = [5, 2, -1, -8, 15, 4, 1, 4];
+		const byte[8] C = [3, 0, 1, -2, 10, 5, 4, 6];
+		byte[8] d;
+
+		asm{
+			emms;
+			movq MM0, A;
+			movq MM1, B;
+			pavgb MM0, MM1;
+			movq d, MM0;
+		}
+
+		for(size_t i = 0; i < C.length; i++){
+			if(d[i] != C[i]){
+				assert(0);
+			}
+		}
+
+		return 0;
+	}
+}else{
+	pragma(msg, "DSTRESS{XFAIL}: no inline ASM support");
+	static assert(0);
+}
diff -r cddb4604d6d7 -r 26f680ab52cd run/a/asm_pavgb_01_B.d
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/run/a/asm_pavgb_01_B.d	Mon May 22 20:15:24 2006 +0000
@@ -0,0 +1,42 @@
+// $HeadURL$
+// $Date$
+// $Author$
+
+module dstress.run.a.asm_pavgb_01_B;
+
+version(D_InlineAsm_X86){
+	version = runTest;
+}else version(D_InlineAsm_X86_64){
+	version = runTest;
+}
+
+version(runTest){
+	import addon.cpuinfo;
+	
+	int main(){
+		haveSSE!()();
+
+		const byte[16] A = [1, -2, 3, 4, 5, 6, 7, 8, -12];
+		const byte[16] B = [5, 2, -1, -8, 15, 4, 1, 4, -6];
+		const byte[16] C = [3, 0, 1, -2, 10, 5, 4, 6, -8];
+		byte[16] d;
+
+		asm{
+			movdqu XMM0, A;
+			movdqu XMM1, B;
+			pavgb XMM0, XMM1;
+			movdqu d, XMM0;
+		}
+
+		for(size_t i = 0; i < C.length; i++){
+			if(d[i] != C[i]){
+				assert(0);
+			}
+		}
+
+		return 0;
+	}
+}else{
+	pragma(msg, "DSTRESS{XFAIL}: no inline ASM support");
+	static assert(0);
+}
diff -r cddb4604d6d7 -r 26f680ab52cd run/a/asm_pavgusb_01_A.d
--- a/run/a/asm_pavgusb_01_A.d	Mon May 22 20:15:07 2006 +0000
+++ b/run/a/asm_pavgusb_01_A.d	Mon May 22 20:15:24 2006 +0000
@@ -4,8 +4,18 @@
 
 module dstress.run.a.asm_pavgusb_01_A;
 
-int main(){
-	version(D_InlineAsm_X86){
+version(D_InlineAsm_X86){
+	version = runTest;
+}else version(D_InlineAsm_X86_64){
+	version = runTest;
+}
+
+version(runTest){
+	import addon.cpuinfo;
+	
+	int main(){
+		haveSSE!()();
+
 		const ubyte[8] A = [1, 2, 3, 4, 5, 6, 7, 8];
 		const ubyte[8] B = [5, 2, 1, 8, 15, 4, 1, 4];
 		const ubyte[8] C = [3, 2, 2, 6, 10, 5, 4, 6];
@@ -25,8 +35,8 @@
 		}
 
 		return 0;
-	}else{
-		pragma(msg, "no Inline asm support");
-		static assert(0);
 	}
+}else{
+	pragma(msg, "DSTRESS{XFAIL}: no inline ASM support");
+	static assert(0);
 }
diff -r cddb4604d6d7 -r 26f680ab52cd run/a/asm_pavgw_01_A.d
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/run/a/asm_pavgw_01_A.d	Mon May 22 20:15:24 2006 +0000
@@ -0,0 +1,42 @@
+// $HeadURL$
+// $Date$
+// $Author$
+
+module dstress.run.a.asm_pavgw_01_A;
+
+version(D_InlineAsm_X86){
+	version = runTest;
+}else version(D_InlineAsm_X86_64){
+	version = runTest;
+}
+
+version(runTest){
+	import addon.cpuinfo;
+	
+	int main(){
+		haveSSE!()();
+
+		const short[8] A = [1, -2, 3, 4, 5, 6, 7, 8];
+		const short[8] B = [5, 2, -1, -8, 15, 4, 1, 4];
+		const short[8] C = [3, 0, 1, -2, 10, 5, 4, 6];
+		byte[8] d;
+
+		asm{
+			movdqu XMM0, A;
+			movdqu XMM1, B;
+			pavgw XMM0, XMM1;
+			movdqu d, XMM0;
+		}
+
+		for(size_t i = 0; i < C.length; i++){
+			if(d[i] != C[i]){
+				assert(0);
+			}
+		}
+
+		return 0;
+	}
+}else{
+	pragma(msg, "DSTRESS{XFAIL}: no inline ASM support");
+	static assert(0);
+}
diff -r cddb4604d6d7 -r 26f680ab52cd run/a/asm_pcmpeqb_01_A.d
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/run/a/asm_pcmpeqb_01_A.d	Mon May 22 20:15:24 2006 +0000
@@ -0,0 +1,83 @@
+// $HeadURL$
+// $Date$
+// $Author$
+
+module dstress.run.a.asm_pcmpeqb_01_A;
+
+version(D_InlineAsm_X86){
+	version = runTest;
+}else version(D_InlineAsm_X86_64){
+	version = runTest;
+}
+
+version(runTest){
+	import addon.cpuinfo;
+	
+	int main(){
+		haveSSE2!()();
+
+		static byte[16] A = [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16];
+		static byte[16] B = [1, 0, byte.min, -5, -4, -3, -2, -1, 0, 1, 2, 3, 4, 5, 6, 16];
+		ubyte[16] c;
+				
+		asm{
+			movdqu XMM0, A;
+			movdqu XMM1, B;
+			pcmpeqb XMM0, XMM1;
+			movdqu c, XMM0;
+		}
+
+		if(c[0] != 0xFF){
+			assert(0);
+		}
+		if(c[1] != 0){
+			assert(0);
+		}
+		if(c[2] != 0){
+			assert(0);
+		}
+		if(c[3] != 0){
+			assert(0);
+		}
+		if(c[4] != 0){
+			assert(0);
+		}
+		if(c[5] != 0){
+			assert(0);
+		}
+		if(c[6] != 0){
+			assert(0);
+		}
+		if(c[7] != 0){
+			assert(0);
+		}
+		if(c[8] != 0){
+			assert(0);
+		}
+		if(c[9] != 0){
+			assert(0);
+		}
+		if(c[10] != 0){
+			assert(0);
+		}
+		if(c[11] != 0){
+			assert(0);
+		}
+		if(c[12] != 0){
+			assert(0);
+		}
+		if(c[13] != 0){
+			assert(0);
+		}
+		if(c[14] != 0){
+			assert(0);
+		}
+		if(c[15] != 0xFF){
+			assert(0);
+		}
+		return 0;
+	}
+}else{
+	pragma(msg, "DSTRESS{XFAIL}: no inline ASM support");
+	static assert(0);
+}
diff -r cddb4604d6d7 -r 26f680ab52cd run/a/asm_pcmpeqd_01_A.d
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/run/a/asm_pcmpeqd_01_A.d	Mon May 22 20:15:24 2006 +0000
@@ -0,0 +1,47 @@
+// $HeadURL$
+// $Date$
+// $Author$
+
+module dstress.run.a.asm_pcmpeqd_01_A;
+
+version(D_InlineAsm_X86){
+	version = runTest;
+}else version(D_InlineAsm_X86_64){
+	version = runTest;
+}
+
+version(runTest){
+	import addon.cpuinfo;
+	
+	int main(){
+		haveSSE2!()();
+
+		static int[4] A = [0, 1, 0, 4];
+		static int[4] B = [0, 3, 1, 4];
+		uint[4] c;
+				
+		asm{
+			movdqu XMM0, A;
+			movdqu XMM1, B;
+			pcmpeqd XMM0, XMM1;
+			movdqu c, XMM0;
+		}
+
+		if(c[0] != 0xFFFF_FFFF){
+			assert(0);
+		}
+		if(c[1] != 0){
+			assert(0);
+		}
+		if(c[2] != 0){
+			assert(0);
+		}
+		if(c[3] != 0xFFFF_FFFF){
+			assert(0);
+		}
+		return 0;
+	}
+}else{
+	pragma(msg, "DSTRESS{XFAIL}: no inline ASM support");
+	static assert(0);
+}
diff -r cddb4604d6d7 -r 26f680ab52cd run/a/asm_pcmpeqw_01_A.d
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/run/a/asm_pcmpeqw_01_A.d	Mon May 22 20:15:24 2006 +0000
@@ -0,0 +1,59 @@
+// $HeadURL$
+// $Date$
+// $Author$
+
+module dstress.run.a.asm_pcmpeqw_01_A;
+
+version(D_InlineAsm_X86){
+	version = runTest;
+}else version(D_InlineAsm_X86_64){
+	version = runTest;
+}
+
+version(runTest){
+	import addon.cpuinfo;
+	
+	int main(){
+		haveSSE2!()();
+
+		static short[8] A = [1, 2, 3, 4, 5, 6, 7, 8];
+		static short[8] B = [1, 0, byte.min, -5, -4, -3, -2, 8];
+		ushort[8] c;
+				
+		asm{
+			movdqu XMM0, A;
+			movdqu XMM1, B;
+			pcmpeqw XMM0, XMM1;
+			movdqu c, XMM0;
+		}
+
+		if(c[0] != 0xFFFF){
+			assert(0);
+		}
+		if(c[1] != 0){
+			assert(0);
+		}
+		if(c[2] != 0){
+			assert(0);
+		}
+		if(c[3] != 0){
+			assert(0);
+		}
+		if(c[4] != 0){
+			assert(0);
+		}
+		if(c[5] != 0){
+			assert(0);
+		}
+		if(c[6] != 0){
+			assert(0);
+		}
+		if(c[7] != 0xFFFF){
+			assert(0);
+		}
+		return 0;
+	}
+}else{
+	pragma(msg, "DSTRESS{XFAIL}: no inline ASM support");
+	static assert(0);
+}
diff -r cddb4604d6d7 -r 26f680ab52cd run/a/asm_pcmpgtb_01_A.d
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/run/a/asm_pcmpgtb_01_A.d	Mon May 22 20:15:24 2006 +0000
@@ -0,0 +1,83 @@
+// $HeadURL$
+// $Date$
+// $Author$
+
+module dstress.run.a.asm_pcmpgtb_01_A;
+
+version(D_InlineAsm_X86){
+	version = runTest;
+}else version(D_InlineAsm_X86_64){
+	version = runTest;
+}
+
+version(runTest){
+	import addon.cpuinfo;
+	
+	int main(){
+		haveSSE2!()();
+
+		static byte[16] A = [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16];
+		static byte[16] B = [1, 3, 2, 4, 6, 5, 7, 9, 8, 10, 12, 11, 13, 16, 15, 14];
+		ubyte[16] c;
+				
+		asm{
+			movdqu XMM0, A;
+			movdqu XMM1, B;
+			pcmpgtb XMM0, XMM1;
+			movdqu c, XMM0;
+		}
+
+		if(c[0] != 0){
+			assert(0);
+		}
+		if(c[1] != 0){
+			assert(0);
+		}
+		if(c[2] != 0xFF){
+			assert(0);
+		}
+		if(c[3] != 0){
+			assert(0);
+		}
+		if(c[4] != 0){
+			assert(0);
+		}
+		if(c[5] != 0xFF){
+			assert(0);
+		}
+		if(c[6] != 0){
+			assert(0);
+		}
+		if(c[7] != 0){
+			assert(0);
+		}
+		if(c[8] != 0xFF){
+			assert(0);
+		}
+		if(c[9] != 0){
+			assert(0);
+		}
+		if(c[10] != 0){
+			assert(0);
+		}
+		if(c[11] != 0xFF){
+			assert(0);
+		}
+		if(c[12] != 0){
+			assert(0);
+		}
+		if(c[13] != 0){
+			assert(0);
+		}
+		if(c[14] != 0){
+			assert(0);
+		}
+		if(c[15] != 0xFF){
+			assert(0);
+		}
+		return 0;
+	}
+}else{
+	pragma(msg, "DSTRESS{XFAIL}: no inline ASM support");
+	static assert(0);
+}
diff -r cddb4604d6d7 -r 26f680ab52cd run/a/asm_pcmpgtd_01_A.d
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/run/a/asm_pcmpgtd_01_A.d	Mon May 22 20:15:24 2006 +0000
@@ -0,0 +1,47 @@
+// $HeadURL$
+// $Date$
+// $Author$
+
+module dstress.run.a.asm_pcmpgtd_01_A;
+
+version(D_InlineAsm_X86){
+	version = runTest;
+}else version(D_InlineAsm_X86_64){
+	version = runTest;
+}
+
+version(runTest){
+	import addon.cpuinfo;
+	
+	int main(){
+		haveSSE2!()();
+
+		static int[4] A = [0, 3, 0, 4];
+		static int[4] B = [0, 1, 1, 4];
+		uint[4] c;
+				
+		asm{
+			movdqu XMM0, A;
+			movdqu XMM1, B;
+			pcmpgtd XMM0, XMM1;
+			movdqu c, XMM0;
+		}
+
+		if(c[0] != 0){
+			assert(0);
+		}
+		if(c[1] != 0xFFFF_FFFF){
+			assert(0);
+		}
+		if(c[2] != 0){
+			assert(0);
+		}
+		if(c[3] != 0){
+			assert(0);
+		}
+		return 0;
+	}
+}else{
+	pragma(msg, "DSTRESS{XFAIL}: no inline ASM support");
+	static assert(0);
+}
diff -r cddb4604d6d7 -r 26f680ab52cd run/a/asm_pcmpgtw_01_A.d
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/run/a/asm_pcmpgtw_01_A.d	Mon May 22 20:15:24 2006 +0000
@@ -0,0 +1,59 @@
+// $HeadURL$
+// $Date$
+// $Author$
+
+module dstress.run.a.asm_pcmpgtw_01_A;
+
+version(D_InlineAsm_X86){
+	version = runTest;
+}else version(D_InlineAsm_X86_64){
+	version = runTest;
+}
+
+version(runTest){
+	import addon.cpuinfo;
+	
+	int main(){
+		haveSSE2!()();
+
+		static short[8] A = [1, 2, 3, 4, 5, 6, 7, 8];
+		static short[8] B = [1, 0, byte.min, -5, -4, -3, -2, 8];
+		ushort[8] c;
+				
+		asm{
+			movdqu XMM0, A;
+			movdqu XMM1, B;
+			pcmpgtw XMM0, XMM1;
+			movdqu c, XMM0;
+		}
+
+		if(c[0] != 0){
+			assert(0);
+		}
+		if(c[1] != 0xFFFF){
+			assert(0);
+		}
+		if(c[2] != 0xFFFF){
+			assert(0);
+		}
+		if(c[3] != 0xFFFF){
+			assert(0);
+		}
+		if(c[4] != 0xFFFF){
+			assert(0);
+		}
+		if(c[5] != 0xFFFF){
+			assert(0);
+		}
+		if(c[6] != 0xFFFF){
+			assert(0);
+		}
+		if(c[7] != 0){
+			assert(0);
+		}
+		return 0;
+	}
+}else{
+	pragma(msg, "DSTRESS{XFAIL}: no inline ASM support");
+	static assert(0);
+}
diff -r cddb4604d6d7 -r 26f680ab52cd run/a/asm_pextrw_01_A.d
--- a/run/a/asm_pextrw_01_A.d	Mon May 22 20:15:07 2006 +0000
+++ b/run/a/asm_pextrw_01_A.d	Mon May 22 20:15:24 2006 +0000
@@ -4,8 +4,18 @@
 
 module dstress.run.a.asm_pextrw_01_A;
 
-int main(){
-	version(D_InlineAsm_X86){
+version(D_InlineAsm_X86){
+	version = runTest;
+}else version(D_InlineAsm_X86_64){
+	version = runTest;
+}
+
+version(runTest){
+	import addon.cpuinfo;
+	
+	int main(){
+		haveSSE!()();
+
 		static ushort[8] x = [1, 2, 3, 4, 5, 0xFFFF, 7, 0];
 		uint a;
 		uint b;
@@ -26,8 +36,8 @@
 		}
 
 		return 0;
-	}else{
-		pragma(msg, "no Inline asm support");
-		static assert(0);
 	}
+}else{
+	pragma(msg, "DSTRESS{XFAIL}: no inline ASM support");
+	static assert(0);
 }
diff -r cddb4604d6d7 -r 26f680ab52cd run/a/asm_pextrw_01_B.d
--- a/run/a/asm_pextrw_01_B.d	Mon May 22 20:15:07 2006 +0000
+++ b/run/a/asm_pextrw_01_B.d	Mon May 22 20:15:24 2006 +0000
@@ -4,8 +4,18 @@
 
 module dstress.run.a.asm_pextrw_01_B;
 
-int main(){
-	version(D_InlineAsm_X86){
+version(D_InlineAsm_X86){
+	version = runTest;
+}else version(D_InlineAsm_X86_64){
+	version = runTest;
+}
+
+version(runTest){
+	import addon.cpuinfo;
+	
+	int main(){
+		haveSSE!()();
+
 		ulong x = 0x0500_FFFF_0707_1234;
 		uint a;
 		uint b;
@@ -26,8 +36,8 @@
 		}
 
 		return 0;
-	}else{
-		pragma(msg, "no Inline asm support");
-		static assert(0);
 	}
+}else{
+	pragma(msg, "DSTRESS{XFAIL}: no inline ASM support");
+	static assert(0);
 }
diff -r cddb4604d6d7 -r 26f680ab52cd run/a/asm_pinsrw_01_A.d
--- a/run/a/asm_pinsrw_01_A.d	Mon May 22 20:15:07 2006 +0000
+++ b/run/a/asm_pinsrw_01_A.d	Mon May 22 20:15:24 2006 +0000
@@ -4,8 +4,18 @@
 
 module dstress.run.a.asm_pinsrw_01_A;
 
-int main(){
-	version(D_InlineAsm_X86){
+version(D_InlineAsm_X86){
+	version = runTest;
+}else version(D_InlineAsm_X86_64){
+	version = runTest;
+}
+
+version(runTest){
+	import addon.cpuinfo;
+	
+	int main(){
+		haveSSE!()();
+
 		ulong x = 0x0500_FFFF_0707_1234;
 		ulong y;
 		uint a = 0x1234_5678;
@@ -22,8 +32,8 @@
 		}
 
 		return 0;
-	}else{
-		pragma(msg, "no Inline asm support");
-		static assert(0);
 	}
+}else{
+	pragma(msg, "DSTRESS{XFAIL}: no inline ASM support");
+	static assert(0);
 }
diff -r cddb4604d6d7 -r 26f680ab52cd run/a/asm_pinsrw_01_B.d
--- a/run/a/asm_pinsrw_01_B.d	Mon May 22 20:15:07 2006 +0000
+++ b/run/a/asm_pinsrw_01_B.d	Mon May 22 20:15:24 2006 +0000
@@ -4,8 +4,18 @@
 
 module dstress.run.a.asm_pinsrw_01_B;
 
-int main(){
-	version(D_InlineAsm_X86){
+version(D_InlineAsm_X86){
+	version = runTest;
+}else version(D_InlineAsm_X86_64){
+	version = runTest;
+}
+
+version(runTest){
+	import addon.cpuinfo;
+
+	int main(){
+		haveSSE!()();
+
 		ulong x = 0x0500_FFFF_0707_1234;
 		ulong y;
 		short a = 0x5678;
@@ -21,8 +31,8 @@
 		}
 
 		return 0;
-	}else{
-		pragma(msg, "no Inline asm support");
-		static assert(0);
 	}
+}else{
+	pragma(msg, "DSTRESS{XFAIL}: no inline ASM support");
+	static assert(0);
 }
diff -r cddb4604d6d7 -r 26f680ab52cd run/a/asm_pmaddwd_01_A.d
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/run/a/asm_pmaddwd_01_A.d	Mon May 22 20:15:24 2006 +0000
@@ -0,0 +1,50 @@
+// $HeadURL$
+// $Date$
+// $Author$
+
+module dsterss.run.a.asm_pmaddwd_01_A;
+
+
+version(D_InlineAsm_X86){
+	version = runTest;
+}else version(D_InlineAsm_X86_64){
+	version = runTest;
+}
+
+version(runTest){
+	import addon.cpuinfo;
+
+	int main(){
+		haveSSE2!()();
+		
+		const short[8] A = [1, 2, 3, 4, 5, 6, 16, 1];
+		const short[8] B = [-9, 10, -11, -12, 13, 14, 0xFFF, 2];
+
+		int[4] c;
+
+		asm{
+			movdqu XMM0, A;
+			movdqu XMM1, B;
+			pmaddwd XMM0, XMM1;
+			movdqu c, XMM0;
+		}
+
+		if(c[0] != (1 * -9) + (2 * 10)){
+			assert(0);
+		}
+		if(c[1] != (3 * -11) + (4 * -12)){
+			assert(0);
+		}
+		if(c[2] != (5 * -12) + (6 * 13)){
+			assert(0);
+		}
+		if(c[3] != 0xFFF02){
+			assert(0);
+		}
+
+		return 0;
+	}
+}else{
+	pragma(msg, "DSTRESS{XFAIL}: no inline ASM support");
+	static assert(0);
+}
diff -r cddb4604d6d7 -r 26f680ab52cd run/a/asm_pmaxsw_01_A.d
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/run/a/asm_pmaxsw_01_A.d	Mon May 22 20:15:24 2006 +0000
@@ -0,0 +1,62 @@
+// $HeadURL$
+// $Date$
+// $Author$
+
+module dsterss.run.a.asm_pmaxsw_01_A;
+
+
+version(D_InlineAsm_X86){
+	version = runTest;
+}else version(D_InlineAsm_X86_64){
+	version = runTest;
+}
+
+version(runTest){
+	import addon.cpuinfo;
+
+	int main(){
+		haveSSE!()();
+		
+		const short[8] A = [1, 2, 3, 4, 5, 6, 16, 2];
+		const short[8] B = [-9, 10, -11, -12, 13, 14, 0xFFF, 1];
+
+		short[8] c;
+
+		asm{
+			movdqu XMM0, A;
+			movdqu XMM1, B;
+			pmaxsw XMM0, XMM1;
+			movdqu c, XMM0;
+		}
+
+		if(c[0] != 1){
+			assert(0);
+		}
+		if(c[1] != 10){
+			assert(0);
+		}
+		if(c[2] != 3){
+			assert(0);
+		}
+		if(c[3] != 4){
+			assert(0);
+		}
+		if(c[4] != 13){
+			assert(0);
+		}
+		if(c[5] != 14){
+			assert(0);
+		}
+		if(c[6] != 0xFFF){
+			assert(0);
+		}
+		if(c[7] != 2){
+			assert(0);
+		}
+
+		return 0;
+	}
+}else{
+	pragma(msg, "DSTRESS{XFAIL}: no inline ASM support");
+	static assert(0);
+}
diff -r cddb4604d6d7 -r 26f680ab52cd run/a/asm_pmaxub_01_A.d
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/run/a/asm_pmaxub_01_A.d	Mon May 22 20:15:24 2006 +0000
@@ -0,0 +1,83 @@
+// $HeadURL$
+// $Date$
+// $Author$
+
+module dstress.run.a.asm_pmaxub_01_A;
+
+version(D_InlineAsm_X86){
+	version = runTest;
+}else version(D_InlineAsm_X86_64){
+	version = runTest;
+}
+
+version(runTest){
+	import addon.cpuinfo;
+	
+	int main(){
+		haveSSE!()();
+
+		static ubyte[16] A = [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16];
+		static ubyte[16] B = [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 17];
+		ubyte[16] c;
+				
+		asm{
+			movdqu XMM0, A;
+			movdqu XMM1, B;
+			pmaxub XMM0, XMM1;
+			movdqu c, XMM0;
+		}
+
+		if(c[0] != 15){
+			assert(0);
+		}
+		if(c[1] != 14){
+			assert(0);
+		}
+		if(c[2] != 13){
+			assert(0);
+		}
+		if(c[3] != 12){
+			assert(0);
+		}
+		if(c[4] != 11){
+			assert(0);
+		}
+		if(c[5] != 10){
+			assert(0);
+		}
+		if(c[6] != 9){
+			assert(0);
+		}
+		if(c[7] != 8){
+			assert(0);
+		}
+		if(c[8] != 9){
+			assert(0);
+		}
+		if(c[9] != 10){
+			assert(0);
+		}
+		if(c[10] != 11){
+			assert(0);
+		}
+		if(c[11] != 12){
+			assert(0);
+		}
+		if(c[12] != 13){
+			assert(0);
+		}
+		if(c[13] != 14){
+			assert(0);
+		}
+		if(c[14] != 15){
+			assert(0);
+		}
+		if(c[15] != 17){
+			assert(0);
+		}
+		return 0;
+	}
+}else{
+	pragma(msg, "DSTRESS{XFAIL}: no inline ASM support");
+	static assert(0);
+}
diff -r cddb4604d6d7 -r 26f680ab52cd run/a/asm_pminsub_01_A.d
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/run/a/asm_pminsub_01_A.d	Mon May 22 20:15:24 2006 +0000
@@ -0,0 +1,83 @@
+// $HeadURL$
+// $Date$
+// $Author$
+
+module dstress.run.a.asm_pminub_01_A;
+
+version(D_InlineAsm_X86){
+	version = runTest;
+}else version(D_InlineAsm_X86_64){
+	version = runTest;
+}
+
+version(runTest){
+	import addon.cpuinfo;
+	
+	int main(){
+		haveSSE!()();
+
+		static ubyte[16] A = [15, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16];
+		static ubyte[16] B = [1, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 17];
+		ubyte[16] c;
+				
+		asm{
+			movdqu XMM0, A;
+			movdqu XMM1, B;
+			pminub XMM0, XMM1;
+			movdqu c, XMM0;
+		}
+
+		if(c[0] != 1){
+			assert(0);
+		}
+		if(c[1] != 2){
+			assert(0);
+		}
+		if(c[2] != 3){
+			assert(0);
+		}
+		if(c[3] != 4){
+			assert(0);
+		}
+		if(c[4] != 5){
+			assert(0);
+		}
+		if(c[5] != 6){
+			assert(0);
+		}
+		if(c[6] != 7){
+			assert(0);
+		}
+		if(c[7] != 8){
+			assert(0);
+		}
+		if(c[8] != 7){
+			assert(0);
+		}
+		if(c[9] != 6){
+			assert(0);
+		}
+		if(c[10] != 5){
+			assert(0);
+		}
+		if(c[11] != 4){
+			assert(0);
+		}
+		if(c[12] != 3){
+			assert(0);
+		}
+		if(c[13] != 2){
+			assert(0);
+		}
+		if(c[14] != 1){
+			assert(0);
+		}
+		if(c[15] != 16){
+			assert(0);
+		}
+		return 0;
+	}
+}else{
+	pragma(msg, "DSTRESS{XFAIL}: no inline ASM support");
+	static assert(0);
+}
diff -r cddb4604d6d7 -r 26f680ab52cd run/a/asm_pminsw_01_A.d
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/run/a/asm_pminsw_01_A.d	Mon May 22 20:15:24 2006 +0000
@@ -0,0 +1,61 @@
+// $HeadURL$
+// $Date$
+// $Author$
+
+module dsterss.run.a.asm_pminsw_01_A;
+
+version(D_InlineAsm_X86){
+	version = runTest;
+}else version(D_InlineAsm_X86_64){
+	version = runTest;
+}
+
+version(runTest){
+	import addon.cpuinfo;
+
+	int main(){
+		haveSSE!()();
+		
+		const short[8] A = [1, 2, 3, 4, 5, 6, 16, 2];
+		const short[8] B = [-9, 10, -11, -12, 13, 14, 0xFFF, 1];
+
+		short[8] c;
+
+		asm{
+			movdqu XMM0, A;
+			movdqu XMM1, B;
+			pminsw XMM0, XMM1;
+			movdqu c, XMM0;
+		}
+
+		if(c[0] != -9){
+			assert(0);
+		}
+		if(c[1] != 2){
+			assert(0);
+		}
+		if(c[2] != -11){
+			assert(0);
+		}
+		if(c[3] != -12){
+			assert(0);
+		}
+		if(c[4] != 5){
+			assert(0);
+		}
+		if(c[5] != 6){
+			assert(0);
+		}
+		if(c[6] != 16){
+			assert(0);
+		}
+		if(c[7] != 1){
+			assert(0);
+		}
+
+		return 0;
+	}
+}else{
+	pragma(msg, "DSTRESS{XFAIL}: no inline ASM support");
+	static assert(0);
+}
diff -r cddb4604d6d7 -r 26f680ab52cd run/a/asm_pmulhuw_01_A.d
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/run/a/asm_pmulhuw_01_A.d	Mon May 22 20:15:24 2006 +0000
@@ -0,0 +1,62 @@
+// $HeadURL$
+// $Date$
+// $Author$
+
+module dstress.run.a.asm_pmulhuw_01_A;
+
+version(D_InlineAsm_X86){
+	version = runTest;
+}else version(D_InlineAsm_X86_64){
+	version = runTest;
+}
+
+version(runTest){
+	import addon.cpuinfo;
+
+	int main(){
+		haveSSE!()();
+
+		const ushort[8] A = [1, 2, 0x7FFF, 7, 0x7FF0, 0x7EDC, 3, 0x6BCD];
+		const ushort[8] B = [1, 0, 7, 0x7FFF, 0x00FF, 0x7EDC, 5, 13];
+
+		ushort[8] c;
+
+		asm{
+			movdqu XMM0, A;
+			movdqu XMM1, B;
+			pmulhuw, XMM0, XMM1;
+			movdqu c, XMM0;
+		}
+
+		if(c[0] != 0){
+			assert(0);
+		}
+		if(c[1] != 0){
+			assert(0);
+		}
+		if(c[2] != 3){
+			assert(0);
+		}
+		if(c[3] != 3){
+			assert(0);
+		}
+		if(c[4] != 0x7F){
+			assert(0);
+		}
+		if(c[5] != 0x3EDD){
+			assert(0);
+		}
+		if(c[6] != 0){
+			assert(0);
+		}
+		if(c[7] != 5){
+			assert(0);
+		}
+
+
+		return 0;
+	}
+}else{
+	pragma(msg, "DSTRESS{XFAIL}: no inline ASM support");
+	static assert(0);
+}
diff -r cddb4604d6d7 -r 26f680ab52cd run/a/asm_pmulhw_01_A.d
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/run/a/asm_pmulhw_01_A.d	Mon May 22 20:15:24 2006 +0000
@@ -0,0 +1,62 @@
+// $HeadURL$
+// $Date$
+// $Author$
+
+module dstress.run.a.asm_pmulhw_01_A;
+
+version(D_InlineAsm_X86){
+	version = runTest;
+}else version(D_InlineAsm_X86_64){
+	version = runTest;
+}
+
+version(runTest){
+	import addon.cpuinfo;
+
+	int main(){
+		haveSSE2!()();
+
+		const short[8] A = [-1, 2, 0x7FFF, 7, 0x7FF0, 0x7EDC, 3, -16];
+		const short[8] B = [2, 0, 7, 0x7FFF, 0x00FF, 0x7EDC, 5, 0xABCD];
+
+		ushort[8] c;
+
+		asm{
+			movdqu XMM0, A;
+			movdqu XMM1, B;
+			pmulhw, XMM0, XMM1;
+			movdqu c, XMM0;
+		}
+
+		if(c[0] != 0xFFFF){
+			assert(0);
+		}
+		if(c[1] != 0){
+			assert(0);
+		}
+		if(c[2] != 3){
+			assert(0);
+		}
+		if(c[3] != 3){
+			assert(0);
+		}
+		if(c[4] != 0x7F){
+			assert(0);
+		}
+		if(c[5] != 0x3EDD){
+			assert(0);
+		}
+		if(c[6] != 0){
+			assert(0);
+		}
+		if(c[7] != 0xFFF5){
+			assert(0);
+		}
+
+
+		return 0;
+	}
+}else{
+	pragma(msg, "DSTRESS{XFAIL}: no inline ASM support");
+	static assert(0);
+}
diff -r cddb4604d6d7 -r 26f680ab52cd run/a/pmovmskb_01_A.d
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/run/a/pmovmskb_01_A.d	Mon May 22 20:15:24 2006 +0000
@@ -0,0 +1,43 @@
+// $HeadURL$
+// $Date$
+// $Author$
+
+module dstress.run.a.asm_pmovmskb_01_A;
+
+
+version(D_InlineAsm_X86){
+	version = runTest;
+}else version(D_InlineAsm_X86_64){
+	version = runTest;
+}
+
+version(runTest){
+	import addon.cpuinfo;
+
+	int main(){
+		haveSSE2!()();
+
+		const ubyte Y = 0b1000_0000;
+		const ubyte N = 0b0111_1111;
+
+		const ubyte[16] A = [Y, N, Y, Y, N, N, Y, Y, Y, N, N, N, Y, N, N, Y];
+
+		int b;
+
+		asm{
+			mov EAX, 0x1234_5678;
+			movdqu XMM0, A;
+			pmovmskb EAX, XMM0;
+			mov b, EAX;
+		}
+
+		if(b != 0b1011_0011_1000_1001){
+			assert(0);
+		}
+
+		return 0;
+	}
+}else{
+	pragma(msg, "DSTRESS{XFAIL}: No inline ASM support");
+	static assert(0);
+}