# HG changeset patch
# User Trass3r
# Date 1283388619 -7200
# Node ID fe941d774f4a699bfce1f45361fa6244a63d1ecc
# Parent  352a5164f692177ad51ed1a8532abbb86e4c6066
+ ctfe of assign operations

diff -r 352a5164f692 -r fe941d774f4a dmd/AddAssignExp.d
--- a/dmd/AddAssignExp.d	Thu Sep 02 02:49:29 2010 +0200
+++ b/dmd/AddAssignExp.d	Thu Sep 02 02:50:19 2010 +0200
@@ -1,6 +1,7 @@
 module dmd.AddAssignExp;
 
 import dmd.common;
+import dmd.expression.Add;
 import dmd.BinExp;
 import dmd.Loc;
 import dmd.Expression;
@@ -142,7 +143,7 @@
 	
     override Expression interpret(InterState istate)
 	{
-		assert(false);
+    	return interpretAssignCommon(istate, &Add);
 	}
 	
     override void buildArrayIdent(OutBuffer buf, Expressions arguments)
diff -r 352a5164f692 -r fe941d774f4a dmd/AndAssignExp.d
--- a/dmd/AndAssignExp.d	Thu Sep 02 02:49:29 2010 +0200
+++ b/dmd/AndAssignExp.d	Thu Sep 02 02:50:19 2010 +0200
@@ -1,6 +1,7 @@
 module dmd.AndAssignExp;
 
 import dmd.common;
+import dmd.expression.And;
 import dmd.BinExp;
 import dmd.Loc;
 import dmd.Expression;
@@ -30,7 +31,7 @@
 	
     override Expression interpret(InterState istate)
 	{
-		assert(false);
+    	return interpretAssignCommon(istate, &And);
 	}
 	
     override void buildArrayIdent(OutBuffer buf, Expressions arguments)
diff -r 352a5164f692 -r fe941d774f4a dmd/CatAssignExp.d
--- a/dmd/CatAssignExp.d	Thu Sep 02 02:49:29 2010 +0200
+++ b/dmd/CatAssignExp.d	Thu Sep 02 02:50:19 2010 +0200
@@ -20,6 +20,7 @@
 import dmd.backend.TYM;
 import dmd.backend.mTY;
 
+import dmd.expression.Cat;
 import dmd.expression.Util;
 
 class CatAssignExp : BinExp
@@ -84,7 +85,7 @@
 	
     override Expression interpret(InterState istate)
 	{
-		assert(false);
+    	return interpretAssignCommon(istate, &Cat);
 	}
 
     override Identifier opId()    /* For operator overloading */
diff -r 352a5164f692 -r fe941d774f4a dmd/DivAssignExp.d
--- a/dmd/DivAssignExp.d	Thu Sep 02 02:49:29 2010 +0200
+++ b/dmd/DivAssignExp.d	Thu Sep 02 02:50:19 2010 +0200
@@ -21,6 +21,7 @@
 import dmd.backend.elem;
 import dmd.backend.OPER;
 import dmd.backend.Util;
+import dmd.expression.Div;
 import dmd.expression.Util;
 
 class DivAssignExp : BinExp
@@ -95,7 +96,7 @@
 	
     override Expression interpret(InterState istate)
 	{
-		assert(false);
+    	return interpretAssignCommon(istate, &Div);
 	}
 	
     override void buildArrayIdent(OutBuffer buf, Expressions arguments)
diff -r 352a5164f692 -r fe941d774f4a dmd/MinAssignExp.d
--- a/dmd/MinAssignExp.d	Thu Sep 02 02:49:29 2010 +0200
+++ b/dmd/MinAssignExp.d	Thu Sep 02 02:50:19 2010 +0200
@@ -1,6 +1,7 @@
 module dmd.MinAssignExp;
 
 import dmd.common;
+import dmd.expression.Min;
 import dmd.BinExp;
 import dmd.Loc;
 import dmd.Expression;
@@ -70,7 +71,7 @@
 	
     override Expression interpret(InterState istate)
 	{
-		assert(false);
+    	return interpretAssignCommon(istate, &Min);
 	}
 	
     override void buildArrayIdent(OutBuffer buf, Expressions arguments)
diff -r 352a5164f692 -r fe941d774f4a dmd/ModAssignExp.d
--- a/dmd/ModAssignExp.d	Thu Sep 02 02:49:29 2010 +0200
+++ b/dmd/ModAssignExp.d	Thu Sep 02 02:50:19 2010 +0200
@@ -1,6 +1,7 @@
 module dmd.ModAssignExp;
 
 import dmd.common;
+import dmd.expression.Mod;
 import dmd.BinExp;
 import dmd.Loc;
 import dmd.Expression;
@@ -32,7 +33,7 @@
 	
     override Expression interpret(InterState istate)
 	{
-		assert(false);
+    	return interpretAssignCommon(istate, &Mod);
 	}
 	
     override void buildArrayIdent(OutBuffer buf, Expressions arguments)
diff -r 352a5164f692 -r fe941d774f4a dmd/MulAssignExp.d
--- a/dmd/MulAssignExp.d	Thu Sep 02 02:49:29 2010 +0200
+++ b/dmd/MulAssignExp.d	Thu Sep 02 02:50:19 2010 +0200
@@ -17,6 +17,7 @@
 
 import dmd.backend.elem;
 import dmd.backend.OPER;
+import dmd.expression.Mul;
 import dmd.expression.Util;
 
 class MulAssignExp : BinExp
@@ -87,7 +88,7 @@
 	
     override Expression interpret(InterState istate)
 	{
-		assert(false);
+    	return interpretAssignCommon(istate, &Mul);
 	}
 	
     override void buildArrayIdent(OutBuffer buf, Expressions arguments)
diff -r 352a5164f692 -r fe941d774f4a dmd/OrAssignExp.d
--- a/dmd/OrAssignExp.d	Thu Sep 02 02:49:29 2010 +0200
+++ b/dmd/OrAssignExp.d	Thu Sep 02 02:50:19 2010 +0200
@@ -1,6 +1,7 @@
 module dmd.OrAssignExp;
 
 import dmd.common;
+import dmd.expression.Or;
 import dmd.BinExp;
 import dmd.Loc;
 import dmd.Expression;
@@ -30,7 +31,7 @@
 	
     override Expression interpret(InterState istate)
 	{
-		assert(false);
+    	return interpretAssignCommon(istate, &Or);
 	}
 	
     override void buildArrayIdent(OutBuffer buf, Expressions arguments)
diff -r 352a5164f692 -r fe941d774f4a dmd/ShlAssignExp.d
--- a/dmd/ShlAssignExp.d	Thu Sep 02 02:49:29 2010 +0200
+++ b/dmd/ShlAssignExp.d	Thu Sep 02 02:50:19 2010 +0200
@@ -13,6 +13,7 @@
 import dmd.Type;
 import dmd.backend.elem;
 import dmd.backend.OPER;
+import dmd.expression.Shl;
 import dmd.expression.Util;
 
 class ShlAssignExp : BinExp
@@ -47,7 +48,7 @@
 	
     override Expression interpret(InterState istate)
 	{
-		assert(false);
+    	return interpretAssignCommon(istate, &Shl);
 	}
 
     override Identifier opId()    /* For operator overloading */
diff -r 352a5164f692 -r fe941d774f4a dmd/ShrAssignExp.d
--- a/dmd/ShrAssignExp.d	Thu Sep 02 02:49:29 2010 +0200
+++ b/dmd/ShrAssignExp.d	Thu Sep 02 02:50:19 2010 +0200
@@ -15,6 +15,7 @@
 import dmd.backend.elem;
 import dmd.backend.OPER;
 
+import dmd.expression.Shr;
 import dmd.expression.Util;
 
 class ShrAssignExp : BinExp
@@ -49,7 +50,7 @@
 	
     override Expression interpret(InterState istate)
 	{
-		assert(false);
+    	return interpretAssignCommon(istate, &Shr);
 	}
 
     override Identifier opId()    /* For operator overloading */
diff -r 352a5164f692 -r fe941d774f4a dmd/UshrAssignExp.d
--- a/dmd/UshrAssignExp.d	Thu Sep 02 02:49:29 2010 +0200
+++ b/dmd/UshrAssignExp.d	Thu Sep 02 02:50:19 2010 +0200
@@ -12,6 +12,7 @@
 import dmd.TOK;
 import dmd.Type;
 import dmd.backend.elem;
+import dmd.expression.Ushr;
 import dmd.expression.Util;
 
 class UshrAssignExp : BinExp
@@ -45,7 +46,7 @@
 	
     override Expression interpret(InterState istate)
 	{
-		assert(false);
+    	return interpretAssignCommon(istate, &Ushr);
 	}
 
     override Identifier opId()    /* For operator overloading */
diff -r 352a5164f692 -r fe941d774f4a dmd/XorAssignExp.d
--- a/dmd/XorAssignExp.d	Thu Sep 02 02:49:29 2010 +0200
+++ b/dmd/XorAssignExp.d	Thu Sep 02 02:50:19 2010 +0200
@@ -1,6 +1,7 @@
 module dmd.XorAssignExp;
 
 import dmd.common;
+import dmd.expression.Xor;
 import dmd.BinExp;
 import dmd.Loc;
 import dmd.Expression;
@@ -29,7 +30,7 @@
 	
     override Expression interpret(InterState istate)
 	{
-		assert(false);
+    	return interpretAssignCommon(istate, &Xor);
 	}
 	
     override void buildArrayIdent(OutBuffer buf, Expressions arguments)